From be5ed35871abb7e561e5c7203333f6aa44357181 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 28 Feb 2020 09:46:54 +0100 Subject: [PATCH] targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets). --- litex_boards/targets/camlink_4k.py | 10 +++++++--- litex_boards/targets/colorlight_5a_75b.py | 5 ++++- litex_boards/targets/hadbadge.py | 8 ++++++-- litex_boards/targets/orangecrab.py | 9 +++++---- litex_boards/targets/trellisboard.py | 9 +++++---- litex_boards/targets/ulx3s.py | 14 +++++++++----- litex_boards/targets/versa_ecp5.py | 8 +++----- 7 files changed, 39 insertions(+), 24 deletions(-) diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index b1b8e31..e6276aa 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -11,6 +11,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import camlink_4k +from litex.build.lattice.trellis import trellis_args, trellis_argdict + from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -93,15 +95,17 @@ class BaseSoC(SoCSDRAM): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Cam Link 4K") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond", - help='gateware toolchain to use, diamond (default) or trellis') + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", + help='gateware toolchain to use, trellis (default) or diamond') builder_args(parser) soc_sdram_args(parser) + trellis_args(parser) args = parser.parse_args() soc = BaseSoC(toolchain=args.toolchain, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build(toolchain_path="/usr/local/diamond/3.10_x64/bin/lin64") + builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} + builder.build(**builder_kargs) if __name__ == "__main__": main() diff --git a/litex_boards/targets/colorlight_5a_75b.py b/litex_boards/targets/colorlight_5a_75b.py index a5906f9..3e56d52 100755 --- a/litex_boards/targets/colorlight_5a_75b.py +++ b/litex_boards/targets/colorlight_5a_75b.py @@ -23,6 +23,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import colorlight_5a_75b +from litex.build.lattice.trellis import trellis_args, trellis_argdict + from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * @@ -125,6 +127,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Colorlight 5A-75B") builder_args(parser) soc_core_args(parser) + trellis_args(parser) parser.add_argument("--revision", default="7.0", type=str, help="Board revision 7.0 (default) or 6.1") parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support") parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)") @@ -139,7 +142,7 @@ def main(): else: soc = BaseSoC(args.revision, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(**trellis_argdict(args)) if __name__ == "__main__": main() diff --git a/litex_boards/targets/hadbadge.py b/litex_boards/targets/hadbadge.py index 58f51c7..d33ee91 100755 --- a/litex_boards/targets/hadbadge.py +++ b/litex_boards/targets/hadbadge.py @@ -14,6 +14,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import hadbadge +from litex.build.lattice.trellis import trellis_args, trellis_argdict + from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -70,18 +72,20 @@ class BaseSoC(SoCSDRAM): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Hackaday Badge") parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", - help='gateware toolchain to use, diamond or trellis (default)') + help='gateware toolchain to use, trellis (default) or diamond') parser.add_argument("--sys-clk-freq", default=48e6, help="system clock frequency (default=48MHz)") builder_args(parser) soc_sdram_args(parser) + trellis_args(parser) args = parser.parse_args() soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} + builder.build(**builder_kargs) if __name__ == "__main__": main() diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 4d0d914..2d05662 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -75,7 +75,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(48e6), toolchain="diamond", **kwargs): + def __init__(self, sys_clk_freq=int(48e6), toolchain="trellis", **kwargs): platform = orangecrab.Platform(toolchain=toolchain) # SoCSDRAM --------------------------------------------------------------------------------- @@ -100,8 +100,8 @@ class BaseSoC(SoCSDRAM): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond", - help='gateware toolchain to use, diamond (default) or trellis') + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", + help="gateware toolchain to use, diamond (default) or trellis") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) @@ -111,7 +111,8 @@ def main(): soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build(**trellis_argdict(args)) + builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} + builder.build(**builder_kargs) if __name__ == "__main__": main() diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index dcd29e2..9963e18 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -108,7 +108,7 @@ class EthernetSoC(BaseSoC): } mem_map.update(BaseSoC.mem_map) - def __init__(self, toolchain="diamond", **kwargs): + def __init__(self, toolchain="trellis", **kwargs): BaseSoC.__init__(self, toolchain=toolchain, **kwargs) # Ethernet --------------------------------------------------------------------------------- @@ -136,8 +136,8 @@ class EthernetSoC(BaseSoC): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Trellis Board") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond", - help='gateware toolchain to use, diamond (default) or trellis') + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", + help="gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) @@ -150,7 +150,8 @@ def main(): cls = EthernetSoC if args.with_ethernet else BaseSoC soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build(**trellis_argdict(args)) + builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} + builder.build(**builder_kargs) if __name__ == "__main__": main() diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py index 5ba068f..8f758dd 100755 --- a/litex_boards/targets/ulx3s.py +++ b/litex_boards/targets/ulx3s.py @@ -12,6 +12,8 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.platforms import ulx3s +from litex.build.lattice.trellis import trellis_args, trellis_argdict + from litex.soc.cores.clock import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -50,7 +52,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, device="LFE5U-45F", toolchain="diamond", + def __init__(self, device="LFE5U-45F", toolchain="trellis", sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", **kwargs): platform = ulx3s.Platform(device=device, toolchain=toolchain) @@ -72,16 +74,17 @@ class BaseSoC(SoCSDRAM): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond", - help='gateware toolchain to use, diamond (default) or trellis') + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", + help="gateware toolchain to use, trellis (default) or diamond") parser.add_argument("--device", dest="device", default="LFE5U-45F", - help='FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F') + help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F") parser.add_argument("--sys-clk-freq", default=50e6, help="system clock frequency (default=50MHz)") parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)") builder_args(parser) soc_sdram_args(parser) + trellis_args(parser) args = parser.parse_args() soc = BaseSoC(device=args.device, toolchain=args.toolchain, @@ -89,7 +92,8 @@ def main(): sdram_module_cls=args.sdram_module, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} + builder.build(**builder_kargs) if __name__ == "__main__": main() diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index 29d8ef3..6065473 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -130,8 +130,8 @@ class EthernetSoC(BaseSoC): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond", - help='gateware toolchain to use, diamond (default) or trellis') + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", + help="gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) @@ -144,9 +144,7 @@ def main(): cls = EthernetSoC if args.with_ethernet else BaseSoC soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder_kargs = {} - if args.toolchain == "trellis": - builder_kargs == trellis_argdict(args) + builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} builder.build(**builder_kargs) if __name__ == "__main__":