diff --git a/litex_boards/partner/targets/hadbadge.py b/litex_boards/partner/targets/hadbadge.py
index 35b9dc5..46bc8a1 100755
--- a/litex_boards/partner/targets/hadbadge.py
+++ b/litex_boards/partner/targets/hadbadge.py
@@ -40,7 +40,7 @@ class _CRG(Module):
         pll.register_clkin(clk8, 8e6)
         pll.create_clkout(self.cd_sys,    sys_clk_freq, phase=11)
         pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=20)
-        self.specials += AsyncResetSynchronizer(self.cd_sys, ~por_done | ~pll.locked)
+        self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll.locked)
 
         # SDRAM clock
         self.comb += platform.request("sdram_clock").eq(self.cd_sys_ps.clk)