diff --git a/litex_boards/platforms/qmtech_xc7a35t.py b/litex_boards/platforms/qmtech_xc7a35t.py
index 7fb34c5..3d3e5d4 100644
--- a/litex_boards/platforms/qmtech_xc7a35t.py
+++ b/litex_boards/platforms/qmtech_xc7a35t.py
@@ -167,6 +167,7 @@ class Platform(XilinxPlatform):
         self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 15]")
         self.add_platform_command("set_property CFGBVS VCCO [current_design]")
         self.add_platform_command("set_property CONFIG_VOLTAGE 3.3 [current_design]")
+        self.toolchain.symbiflow_device = device
 
     def create_programmer(self):
         bscan_spi = "bscan_spi_xc7a35t.bit"
diff --git a/litex_boards/targets/qmtech_xc7a35t.py b/litex_boards/targets/qmtech_xc7a35t.py
index 804305e..c57e5e5 100755
--- a/litex_boards/targets/qmtech_xc7a35t.py
+++ b/litex_boards/targets/qmtech_xc7a35t.py
@@ -143,7 +143,7 @@ class BaseSoC(SoCCore):
 # Build --------------------------------------------------------------------------------------------
 
 def main():
-    parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
+    parser = argparse.ArgumentParser(description="LiteX SoC on QMTech XC7A35T")
     parser.add_argument("--toolchain",           default="vivado",                 help="Toolchain use to build (default: vivado)")
     parser.add_argument("--build",               action="store_true",              help="Build bitstream")
     parser.add_argument("--load",                action="store_true",              help="Load bitstream")