From c05c494a82dda29f5650bd8e5ac7e2feccdfb6fe Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 5 May 2023 09:43:19 +0200 Subject: [PATCH] targets/mnt_rkx7/usb_ohci: Use SoC.bus if SoC does not have a DMA bus. --- litex_boards/targets/mnt_rkx7.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex_boards/targets/mnt_rkx7.py b/litex_boards/targets/mnt_rkx7.py index fcc2363..8ee2925 100755 --- a/litex_boards/targets/mnt_rkx7.py +++ b/litex_boards/targets/mnt_rkx7.py @@ -173,7 +173,8 @@ class BaseSoC(SoCCore): if with_usb_host: self.usb_ohci = USBOHCI(platform, platform.request("usb")) self.bus.add_slave("usb_ohci_ctrl", self.usb_ohci.wb_ctrl, region=SoCRegion(origin=self.mem_map["usb_ohci"], size=0x100000, cached=False)) - self.dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma) + dma_bus = getattr(self, "dma_bus", self.bus) + dma_bus.add_master("usb_ohci_dma", master=self.usb_ohci.wb_dma) self.comb += self.cpu.interrupt[16].eq(self.usb_ohci.interrupt) # LiteScope UART