From e71e3ab3ec5c1c7430dd384b7846bfd96d555c05 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sat, 3 Dec 2022 16:08:03 +0100 Subject: [PATCH 1/2] platforms,targets/digilent_arty_z7: use a dict for PS config instead of fetching file configuration --- litex_boards/platforms/digilent_arty_z7.py | 42 ++++++++++++++++++++++ litex_boards/targets/digilent_arty_z7.py | 9 ++--- 2 files changed, 47 insertions(+), 4 deletions(-) diff --git a/litex_boards/platforms/digilent_arty_z7.py b/litex_boards/platforms/digilent_arty_z7.py index f51282b..6af8757 100644 --- a/litex_boards/platforms/digilent_arty_z7.py +++ b/litex_boards/platforms/digilent_arty_z7.py @@ -209,6 +209,47 @@ _connectors = [ }) ] +# PS7 config --------------------------------------------------------------------------------------- + +ps7_config = { + "PCW_PRESET_BANK1_VOLTAGE" : "LVCMOS 1.8V", + "PCW_CRYSTAL_PERIPHERAL_FREQMHZ" : "50", + "PCW_APU_PERIPHERAL_FREQMHZ" : "650", + "PCW_SDIO_PERIPHERAL_FREQMHZ" : "50", + "PCW_FPGA0_PERIPHERAL_FREQMHZ" : "100", + "PCW_UIPARAM_DDR_FREQ_MHZ" : "525", + "PCW_UIPARAM_DDR_BUS_WIDTH" : "16 Bit", + "PCW_UIPARAM_DDR_PARTNO" : "MT41J256M16 RE-125", + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0" : "0.040", + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1" : "0.058", + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2" : "-0.009", + "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3" : "-0.033", + "PCW_UIPARAM_DDR_BOARD_DELAY0" : "0.223", + "PCW_UIPARAM_DDR_BOARD_DELAY1" : "0.212", + "PCW_UIPARAM_DDR_BOARD_DELAY2" : "0.085", + "PCW_UIPARAM_DDR_BOARD_DELAY3" : "0.092", + "PCW_QSPI_PERIPHERAL_ENABLE" : "1", + "PCW_QSPI_GRP_SINGLE_SS_ENABLE" : "1", + "PCW_QSPI_GRP_FBCLK_ENABLE" : "1", + "PCW_ENET0_PERIPHERAL_ENABLE" : "1", + "PCW_ENET0_ENET0_IO" : "MIO 16 .. 27", + "PCW_ENET0_GRP_MDIO_ENABLE" : "1", + "PCW_ENET0_GRP_MDIO_IO" : "MIO 52 .. 53", + "PCW_ENET0_RESET_ENABLE" : "1", + "PCW_ENET0_RESET_IO" : "MIO 9", + "PCW_SD0_PERIPHERAL_ENABLE" : "1", + "PCW_SD0_GRP_CD_ENABLE" : "1", + "PCW_SD0_GRP_CD_IO" : "MIO 47", + "PCW_UART0_PERIPHERAL_ENABLE" : "1", + "PCW_UART0_UART0_IO" : "MIO 14 .. 15", + "PCW_USB0_PERIPHERAL_ENABLE" : "1", + "PCW_USB0_RESET_ENABLE" : "1", + "PCW_USB0_RESET_IO" : "MIO 46", + "PCW_GPIO_MIO_GPIO_ENABLE" : "1", + "PCW_GPIO_MIO_GPIO_IO" : "MIO", + "PCW_GPIO_EMIO_GPIO_ENABLE" : "0", +} + # Platform ----------------------------------------------------------------------------------------- class Platform(Xilinx7SeriesPlatform): @@ -226,6 +267,7 @@ class Platform(Xilinx7SeriesPlatform): }[variant] Xilinx7SeriesPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain) + self.ps7_config = ps7_config def create_programmer(self): return VivadoProgrammer() diff --git a/litex_boards/targets/digilent_arty_z7.py b/litex_boards/targets/digilent_arty_z7.py index 68a81d5..47b0ce5 100755 --- a/litex_boards/targets/digilent_arty_z7.py +++ b/litex_boards/targets/digilent_arty_z7.py @@ -75,10 +75,11 @@ class BaseSoC(SoCCore): if kwargs.get("cpu_type", None) == "zynq7000": assert toolchain == "vivado", ' not tested / specific vivado cmds' - preset_name = "arty_z7_20.tcl" if variant == "z7-20" else "arty_z7_10.tcl" - - os.system("wget http://kmf2.trabucayre.com/" + preset_name) - self.cpu.set_ps7(preset=preset_name) + self.cpu.set_ps7(name="Zynq", + config={ + **platform.ps7_config, + "PCW_FPGA0_PERIPHERAL_FREQMHZ" : sys_clk_freq / 1e6, + }) # Connect AXI GP0 to the SoC wb_gp0 = wishbone.Interface() From a889321535c7bfe8c814033774f60eb81ed670b8 Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Sat, 3 Dec 2022 16:14:28 +0100 Subject: [PATCH 2/2] targets/digilent_arty_z7: adding note to load gateware and bios --- litex_boards/targets/digilent_arty_z7.py | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/litex_boards/targets/digilent_arty_z7.py b/litex_boards/targets/digilent_arty_z7.py index 47b0ce5..dd9d387 100755 --- a/litex_boards/targets/digilent_arty_z7.py +++ b/litex_boards/targets/digilent_arty_z7.py @@ -6,6 +6,26 @@ # Copyright (c) 2021 Gwenhael Goavec-Merou # SPDX-License-Identifier: BSD-2-Clause +# Load bit/bios ------------------------------------------------------------------------------------ +# +# 1/ tcl script: +# connect +# targets -set -filter {name =~ "ARM*#0"} +# rst +# stop +# +# source build/digilent_arty_z7/gateware/digilent_arty_z7.srcs/sources_1/ip/Zynq/ps7_init.tcl +# ps7_init +# ps7_post_config +# +# dow build/digilent_arty_z7/software/bios/bios.elf +# fpga build/digilent_arty_z7/gateware/digilent_arty_z7.bit +# con +# +# 2/ loading +# xsct -nodisp ps7_boot.tcl +# where ps7_boot.tcl is your script name + from migen import * from litex.gen import LiteXModule