From c0773ed9b97adbee845e824a284ee064d0cfcee9 Mon Sep 17 00:00:00 2001 From: Hans Baier Date: Mon, 16 Jan 2023 11:31:35 +0700 Subject: [PATCH] HPC FPGA Store on AliExpress renamed itself to SITLINV --- .../{hpcstore_xc7k420t.py => sitlinv_xc7k420t.py} | 2 +- .../{hpcstore_xc7k420t.py => sitlinv_xc7k420t.py} | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) rename litex_boards/platforms/{hpcstore_xc7k420t.py => sitlinv_xc7k420t.py} (99%) rename litex_boards/targets/{hpcstore_xc7k420t.py => sitlinv_xc7k420t.py} (94%) diff --git a/litex_boards/platforms/hpcstore_xc7k420t.py b/litex_boards/platforms/sitlinv_xc7k420t.py similarity index 99% rename from litex_boards/platforms/hpcstore_xc7k420t.py rename to litex_boards/platforms/sitlinv_xc7k420t.py index f6a7c2b..e8542e3 100644 --- a/litex_boards/platforms/hpcstore_xc7k420t.py +++ b/litex_boards/platforms/sitlinv_xc7k420t.py @@ -8,7 +8,7 @@ from litex.build.generic_platform import * from litex.build.xilinx import Xilinx7SeriesPlatform from litex.build.openocd import OpenOCD -# Board support for this chinese Kintex 420T board by "HPC FPGA Board Store" +# Board support for this chinese Kintex 420T board by "SITLINV FPGA Board Store" # https://www.aliexpress.com/item/1005001631827738.html # IOs ---------------------------------------------------------------------------------------------- diff --git a/litex_boards/targets/hpcstore_xc7k420t.py b/litex_boards/targets/sitlinv_xc7k420t.py similarity index 94% rename from litex_boards/targets/hpcstore_xc7k420t.py rename to litex_boards/targets/sitlinv_xc7k420t.py index ff7ef62..dc2d86f 100755 --- a/litex_boards/targets/hpcstore_xc7k420t.py +++ b/litex_boards/targets/sitlinv_xc7k420t.py @@ -10,7 +10,7 @@ # Copyright (c) 2020 Hans Baier # SPDX-License-Identifier: BSD-2-Clause -# Board support for this chinese Kintex 420T board by "HPC FPGA Board Store" +# Board support for this chinese Kintex 420T board by "SITLINV FPGA Board Store" # https://www.aliexpress.com/item/1005001631827738.html import os @@ -19,7 +19,7 @@ from migen import * from litex.gen import LiteXModule -from litex_boards.platforms import hpcstore_xc7k420t +from litex_boards.platforms import sitlinv_xc7k420t from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -71,13 +71,13 @@ class BaseSoC(SoCCore): with_pcie = False, with_sata = False, **kwargs): - platform = hpcstore_xc7k420t.Platform(io_voltage) + platform = sitlinv_xc7k420t.Platform(io_voltage) # CRG -------------------------------------------------------------------------------------- self.crg = _CRG(platform, sys_clk_freq) # SoCCore ---------------------------------------------------------------------------------- - SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on HPC Store XC7K420T", **kwargs) + SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on SITLINV XC7K420T", **kwargs) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: @@ -139,7 +139,7 @@ class BaseSoC(SoCCore): def main(): from litex.build.parser import LiteXArgumentParser - parser = LiteXArgumentParser(platform=hpcstore_xc7k420t.Platform, description="LiteX SoC on AliExpress HPC Store XC7K420T") + parser = LiteXArgumentParser(platform=sitlinv_xc7k420t.Platform, description="LiteX SoC on AliExpress SITLINV FPGA Store XC7K420T") parser.add_target_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency.") parser.add_target_argument("--io-voltage", default="3.3V", help="IO voltage chosen by Jumper J3. Can be: '3.3V' or '2.5V'.") parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.")