From c1088befe557ce849d1cb5b4ed0fa91653648803 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 26 Jul 2023 16:56:27 +0200 Subject: [PATCH] targets/CRG: Add rst signal when missing. Allow properly reseting the PLL from the SoC. --- litex_boards/targets/antmicro_datacenter_ddr4_test_board.py | 3 +++ litex_boards/targets/antmicro_lpddr4_test_board.py | 2 ++ litex_boards/targets/antmicro_sdi_mipi_video_converter.py | 2 ++ litex_boards/targets/decklink_intensity_pro_4k.py | 3 ++- litex_boards/targets/decklink_quad_hdmi_recorder.py | 2 ++ litex_boards/targets/efinix_t8f81_dev_kit.py | 3 ++- litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py | 3 ++- litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py | 3 ++- litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py | 3 ++- litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py | 3 ++- litex_boards/targets/efinix_xyloni_dev_kit.py | 3 ++- litex_boards/targets/fairwaves_xtrx.py | 2 ++ litex_boards/targets/jungle_electronics_fireant.py | 3 ++- litex_boards/targets/lattice_crosslink_nx_evn.py | 2 ++ litex_boards/targets/sipeed_tang_primer.py | 5 +++-- litex_boards/targets/sipeed_tang_primer_20k.py | 2 +- litex_boards/targets/xilinx_alveo_u280.py | 2 ++ litex_boards/targets/ztex213.py | 3 ++- 18 files changed, 37 insertions(+), 12 deletions(-) diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py index dcf0495..0aab059 100755 --- a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py +++ b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py @@ -39,6 +39,7 @@ from litespi.opcodes import SpiNorFlashOpCodes as Codes class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq, iodelay_clk_freq, with_video_pll=False): + self.rst = Signal() self.cd_sys = ClockDomain() self.cd_sys2x = ClockDomain() self.cd_sys4x = ClockDomain() @@ -54,6 +55,7 @@ class _CRG(LiteXModule): clk100 = platform.request("clk100") self.pll = pll = S7PLL(speedgrade=-1) + self.comb += pll.reset.eq(self.rst) pll.register_clkin(clk100, 100e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq) @@ -66,6 +68,7 @@ class _CRG(LiteXModule): # Video PLL. if with_video_pll: self.video_pll = video_pll = S7MMCM(speedgrade=-1) + self.comb += video_pll.reset.eq(self.rst) video_pll.register_clkin(clk100, 100e6) video_pll.create_clkout(self.cd_hdmi, 40e6) video_pll.create_clkout(self.cd_hdmi5x, 5*40e6) diff --git a/litex_boards/targets/antmicro_lpddr4_test_board.py b/litex_boards/targets/antmicro_lpddr4_test_board.py index b0285de..55e0e58 100755 --- a/litex_boards/targets/antmicro_lpddr4_test_board.py +++ b/litex_boards/targets/antmicro_lpddr4_test_board.py @@ -27,6 +27,7 @@ from litex.soc.cores.hyperbus import HyperRAM class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq, iodelay_clk_freq): + self.rst = Signal() self.cd_sys = ClockDomain() self.cd_sys2x = ClockDomain() self.cd_sys8x = ClockDomain() @@ -35,6 +36,7 @@ class _CRG(LiteXModule): # # # self.pll = pll = S7PLL(speedgrade=-1) + self.comb += pll.reset.eq(self.rst) pll.register_clkin(platform.request("clk100"), 100e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys2x, 2 * sys_clk_freq) diff --git a/litex_boards/targets/antmicro_sdi_mipi_video_converter.py b/litex_boards/targets/antmicro_sdi_mipi_video_converter.py index b8509ec..3606bcf 100755 --- a/litex_boards/targets/antmicro_sdi_mipi_video_converter.py +++ b/litex_boards/targets/antmicro_sdi_mipi_video_converter.py @@ -32,6 +32,7 @@ mB = 1024*kB class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.cd_por = ClockDomain() self.cd_sys = ClockDomain() @@ -48,6 +49,7 @@ class _CRG(LiteXModule): # PLL self.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True) + self.comb += sys_pll.reset.eq(self.rst) sys_pll.register_clkin(self.cd_por.clk, hf_clk_freq) sys_pll.create_clkout(self.cd_sys, sys_clk_freq) self.specials += AsyncResetSynchronizer(self.cd_sys, ~self.sys_pll.locked | ~por_done) diff --git a/litex_boards/targets/decklink_intensity_pro_4k.py b/litex_boards/targets/decklink_intensity_pro_4k.py index f23693b..03a4e58 100755 --- a/litex_boards/targets/decklink_intensity_pro_4k.py +++ b/litex_boards/targets/decklink_intensity_pro_4k.py @@ -28,12 +28,13 @@ from litepcie.software import generate_litepcie_software class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.cd_sys = ClockDomain() # # # self.pll = pll = S7PLL(speedgrade=-1) - self.comb += pll.reset.eq(ResetSignal("pcie")) + self.comb += pll.reset.eq(ResetSignal("pcie") | self.rst) pll.register_clkin(ClockSignal("pcie"), 125e6) pll.create_clkout(self.cd_sys, sys_clk_freq) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. diff --git a/litex_boards/targets/decklink_quad_hdmi_recorder.py b/litex_boards/targets/decklink_quad_hdmi_recorder.py index f6ed9d9..058f13f 100755 --- a/litex_boards/targets/decklink_quad_hdmi_recorder.py +++ b/litex_boards/targets/decklink_quad_hdmi_recorder.py @@ -36,6 +36,7 @@ from litepcie.software import generate_litepcie_software class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.cd_sys = ClockDomain() self.cd_sys4x = ClockDomain() self.cd_pll4x = ClockDomain() @@ -44,6 +45,7 @@ class _CRG(LiteXModule): # # # self.pll = pll = USMMCM(speedgrade=-2) + self.comb += pll.reset.eq(self.rst) pll.register_clkin(platform.request("clk200"), 200e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) pll.create_clkout(self.cd_idelay, 200e6) diff --git a/litex_boards/targets/efinix_t8f81_dev_kit.py b/litex_boards/targets/efinix_t8f81_dev_kit.py index 6a0e89d..df58150 100755 --- a/litex_boards/targets/efinix_t8f81_dev_kit.py +++ b/litex_boards/targets/efinix_t8f81_dev_kit.py @@ -29,6 +29,7 @@ mB = 1024*kB class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.cd_sys = ClockDomain() # # # @@ -38,7 +39,7 @@ class _CRG(LiteXModule): # PLL. self.pll = pll = TRIONPLL(platform) - self.comb += pll.reset.eq(~rst_n) + self.comb += pll.reset.eq(~rst_n | self.rst) pll.register_clkin(clk33, 33.333e6) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True) diff --git a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py index 5e06616..25e0ef2 100755 --- a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py +++ b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py @@ -28,6 +28,7 @@ from liteeth.phy.titaniumrgmii import LiteEthPHYRGMII class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.cd_sys = ClockDomain() # # # @@ -37,7 +38,7 @@ class _CRG(LiteXModule): # PLL self.pll = pll = TITANIUMPLL(platform) - self.comb += pll.reset.eq(~rst_n) + self.comb += pll.reset.eq(~rst_n | self.rst) pll.register_clkin(clk25, 25e6) # You can use CLKOUT0 only for clocks with a maximum frequency of 4x # (integer) of the reference clock. If all your system clocks do not fall within diff --git a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py index 78ca785..f06dfd4 100755 --- a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py @@ -27,6 +27,7 @@ from liteeth.phy.trionrgmii import LiteEthPHYRGMII class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.cd_sys = ClockDomain() # # # @@ -37,7 +38,7 @@ class _CRG(LiteXModule): # PLL self.pll = pll = TRIONPLL(platform) - self.comb += pll.reset.eq(~rst_n) + self.comb += pll.reset.eq(~rst_n | self.rst) pll.register_clkin(clk40, 40e6) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True, name="axi_clk") diff --git a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py index a742ea8..beb15c0 100755 --- a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py @@ -26,6 +26,7 @@ from litex.soc.cores.led import LedChaser class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.cd_sys = ClockDomain() # # # @@ -35,7 +36,7 @@ class _CRG(LiteXModule): # PLL self.pll = pll = TRIONPLL(platform) - self.comb += pll.reset.eq(~rst_n) + self.comb += pll.reset.eq(~rst_n | self.rst) pll.register_clkin(clk50, 50e6) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True) diff --git a/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py b/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py index 6a82573..e117289 100755 --- a/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py @@ -24,6 +24,7 @@ from litex.soc.cores.led import LedChaser class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.cd_sys = ClockDomain() # # # @@ -33,7 +34,7 @@ class _CRG(LiteXModule): # PLL self.pll = pll = TRIONPLL(platform) - self.comb += pll.reset.eq(~rst_n) + self.comb += pll.reset.eq(~rst_n | self.rst) pll.register_clkin(clk50, 50e6) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True) diff --git a/litex_boards/targets/efinix_xyloni_dev_kit.py b/litex_boards/targets/efinix_xyloni_dev_kit.py index 7d12dee..700d79c 100755 --- a/litex_boards/targets/efinix_xyloni_dev_kit.py +++ b/litex_boards/targets/efinix_xyloni_dev_kit.py @@ -28,6 +28,7 @@ mB = 1024*kB class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.cd_sys = ClockDomain() # # # @@ -37,7 +38,7 @@ class _CRG(LiteXModule): # PLL. self.pll = pll = TRIONPLL(platform) - self.comb += pll.reset.eq(~rst_n) + self.comb += pll.reset.eq(~rst_n | self.rst) pll.register_clkin(clk33, 33.333e6) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True) diff --git a/litex_boards/targets/fairwaves_xtrx.py b/litex_boards/targets/fairwaves_xtrx.py index a443d1a..b23aee2 100755 --- a/litex_boards/targets/fairwaves_xtrx.py +++ b/litex_boards/targets/fairwaves_xtrx.py @@ -45,6 +45,7 @@ from litepcie.software import generate_litepcie_software class CRG(LiteXModule): def __init__(self, platform, sys_clk_freq, with_pcie=False): + self.rst = Signal() self.cd_sys = ClockDomain() # # # @@ -57,6 +58,7 @@ class CRG(LiteXModule): ] else: self.pll = pll = S7PLL(speedgrade=-2) + self.comb += pll.reset.eq(self.rst) pll.register_clkin(platform.request("clk60"), 60e6) pll.create_clkout(self.cd_sys, sys_clk_freq) diff --git a/litex_boards/targets/jungle_electronics_fireant.py b/litex_boards/targets/jungle_electronics_fireant.py index 1a95632..0816b32 100755 --- a/litex_boards/targets/jungle_electronics_fireant.py +++ b/litex_boards/targets/jungle_electronics_fireant.py @@ -32,6 +32,7 @@ mB = 1024*kB class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.cd_sys = ClockDomain() # # # @@ -41,7 +42,7 @@ class _CRG(LiteXModule): # PLL. self.pll = pll = TRIONPLL(platform) - self.comb += pll.reset.eq(~rst_n) + self.comb += pll.reset.eq(~rst_n | self.rst) pll.register_clkin(clk33, 33.333e6) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True) diff --git a/litex_boards/targets/lattice_crosslink_nx_evn.py b/litex_boards/targets/lattice_crosslink_nx_evn.py index b5d822b..6c1a332 100755 --- a/litex_boards/targets/lattice_crosslink_nx_evn.py +++ b/litex_boards/targets/lattice_crosslink_nx_evn.py @@ -32,6 +32,7 @@ mB = 1024*kB class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.cd_por = ClockDomain() self.cd_sys = ClockDomain() @@ -51,6 +52,7 @@ class _CRG(LiteXModule): # PLL self.sys_pll = sys_pll = NXPLL(platform=platform, create_output_port_clocks=True) + self.comb += sys_pll.reset.eq(self.rst) sys_pll.register_clkin(self.cd_por.clk, hf_clk_freq) sys_pll.create_clkout(self.cd_sys, sys_clk_freq) self.specials += AsyncResetSynchronizer(self.cd_sys, ~self.sys_pll.locked | ~por_done ) diff --git a/litex_boards/targets/sipeed_tang_primer.py b/litex_boards/targets/sipeed_tang_primer.py index f6f79be..13a00d5 100755 --- a/litex_boards/targets/sipeed_tang_primer.py +++ b/litex_boards/targets/sipeed_tang_primer.py @@ -25,7 +25,8 @@ from litex.soc.cores.led import LedChaser class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): - self.cd_sys = ClockDomain() + self.rst = Signal() + self.cd_sys = ClockDomain() # # # @@ -34,7 +35,7 @@ class _CRG(LiteXModule): rst_n = platform.request("user_btn", 0) self.comb += self.cd_sys.clk.eq(clk24) - self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n) + self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n | self.rst) # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/sipeed_tang_primer_20k.py b/litex_boards/targets/sipeed_tang_primer_20k.py index 3cd99af..5bb4242 100755 --- a/litex_boards/targets/sipeed_tang_primer_20k.py +++ b/litex_boards/targets/sipeed_tang_primer_20k.py @@ -56,7 +56,7 @@ class _CRG(LiteXModule): # PLL self.pll = pll = GW2APLL(devicename=platform.devicename, device=platform.device) - self.comb += pll.reset.eq(~por_done) + self.comb += pll.reset.eq(~por_done | self.rst) pll.register_clkin(clk27, 27e6) pll.create_clkout(self.cd_sys2x_i, 2*sys_clk_freq) self.specials += [ diff --git a/litex_boards/targets/xilinx_alveo_u280.py b/litex_boards/targets/xilinx_alveo_u280.py index 0cf89e8..d57aa7a 100755 --- a/litex_boards/targets/xilinx_alveo_u280.py +++ b/litex_boards/targets/xilinx_alveo_u280.py @@ -46,6 +46,7 @@ from litescope import LiteScopeAnalyzer class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq, ddram_channel, with_hbm): if with_hbm: + self.rst = Signal() self.cd_sys = ClockDomain() self.cd_hbm_ref = ClockDomain() self.cd_apb = ClockDomain() @@ -60,6 +61,7 @@ class _CRG(LiteXModule): if with_hbm: self.pll = pll = USMMCM(speedgrade=-2) + self.comb += pll.reset.eq(self.rst) pll.register_clkin(platform.request("sysclk", ddram_channel), 100e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_hbm_ref, 100e6) diff --git a/litex_boards/targets/ztex213.py b/litex_boards/targets/ztex213.py index 3a91de3..4cbefdc 100755 --- a/litex_boards/targets/ztex213.py +++ b/litex_boards/targets/ztex213.py @@ -31,6 +31,7 @@ from litedram.phy import s7ddrphy class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): + self.rst = Signal() self.cd_sys = ClockDomain() self.cd_sys4x = ClockDomain() self.cd_sys4x_dqs = ClockDomain() @@ -53,7 +54,7 @@ class _CRG(LiteXModule): self.comb += self.cd_por.clk.eq(clk48) self.comb += por_done.eq(por_count == 0) self.sync.por += If(~por_done, por_count.eq(por_count - 1)) - self.comb += pll.reset.eq(~por_done) + self.comb += pll.reset.eq(~por_done | self.rst) self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)