From c32e790421952dc2459a8a7968403021db06da2a Mon Sep 17 00:00:00 2001
From: Michael Betz <michibetz@gmail.com>
Date: Fri, 19 Feb 2021 22:47:18 -0800
Subject: [PATCH] vc707: fix default clock frequency

---
 litex_boards/platforms/vc707.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/litex_boards/platforms/vc707.py b/litex_boards/platforms/vc707.py
index d4acf02..275e4e8 100644
--- a/litex_boards/platforms/vc707.py
+++ b/litex_boards/platforms/vc707.py
@@ -629,7 +629,7 @@ _connectors = [
 
 class Platform(XilinxPlatform):
     default_clk_name   = "clk156"
-    default_clk_period = 1e9/156.5e6
+    default_clk_period = 1e9/156.25e6
 
     def __init__(self):
         XilinxPlatform.__init__(self, "xc7vx485tffg1761-2", _io, _connectors, toolchain="vivado")