From c3ea04b6e9937beea72a8812336c31e79185af6c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 12 Oct 2020 17:33:40 +0200 Subject: [PATCH] targets/s7/us: update sdram (manual cmd_latency no longer needed). --- litex_boards/targets/alveo_u250.py | 1 - litex_boards/targets/genesys2.py | 3 +-- litex_boards/targets/kc705.py | 3 +-- litex_boards/targets/kcu105.py | 3 +-- litex_boards/targets/kx2.py | 3 +-- litex_boards/targets/mercury_xu5.py | 3 +-- litex_boards/targets/vc707.py | 3 +-- litex_boards/targets/vcu118.py | 3 +-- litex_boards/targets/xcu1525.py | 3 +-- litex_boards/targets/zcu104.py | 3 +-- 10 files changed, 9 insertions(+), 19 deletions(-) diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py index 0374001..3c78841 100755 --- a/litex_boards/targets/alveo_u250.py +++ b/litex_boards/targets/alveo_u250.py @@ -78,7 +78,6 @@ class BaseSoC(SoCCore): memtype = "DDR4", sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6, - cmd_latency = 1, is_rdimm = True) self.add_csr("ddrphy") self.add_sdram("sdram", diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py index e669c8b..74b4611 100755 --- a/litex_boards/targets/genesys2.py +++ b/litex_boards/targets/genesys2.py @@ -63,8 +63,7 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, - sys_clk_freq = sys_clk_freq, - cmd_latency = 1) + sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py index bfb6919..11d0026 100755 --- a/litex_boards/targets/kc705.py +++ b/litex_boards/targets/kc705.py @@ -65,8 +65,7 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, - sys_clk_freq = sys_clk_freq, - cmd_latency = 1) + sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py index 445f83d..5217908 100755 --- a/litex_boards/targets/kcu105.py +++ b/litex_boards/targets/kcu105.py @@ -74,8 +74,7 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), memtype = "DDR4", sys_clk_freq = sys_clk_freq, - iodelay_clk_freq = 200e6, - cmd_latency = 1) + iodelay_clk_freq = 200e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, diff --git a/litex_boards/targets/kx2.py b/litex_boards/targets/kx2.py index e00b80c..575b5f9 100755 --- a/litex_boards/targets/kx2.py +++ b/litex_boards/targets/kx2.py @@ -62,8 +62,7 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, - sys_clk_freq = sys_clk_freq, - cmd_latency = 1) + sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py index eec3bf8..0a99b3d 100755 --- a/litex_boards/targets/mercury_xu5.py +++ b/litex_boards/targets/mercury_xu5.py @@ -71,8 +71,7 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), memtype = "DDR4", sys_clk_freq = sys_clk_freq, - iodelay_clk_freq = 500e6, - cmd_latency = 1) + iodelay_clk_freq = 500e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, diff --git a/litex_boards/targets/vc707.py b/litex_boards/targets/vc707.py index 266c089..13706cc 100755 --- a/litex_boards/targets/vc707.py +++ b/litex_boards/targets/vc707.py @@ -60,8 +60,7 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = s7ddrphy.V7DDRPHY(platform.request("ddram"), memtype = "DDR3", nphases = 4, - sys_clk_freq = sys_clk_freq, - cmd_latency = 1) + sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py index 83ec052..419457b 100755 --- a/litex_boards/targets/vcu118.py +++ b/litex_boards/targets/vcu118.py @@ -71,8 +71,7 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), memtype = "DDR4", sys_clk_freq = sys_clk_freq, - iodelay_clk_freq = 500e6, - cmd_latency = 1) + iodelay_clk_freq = 500e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py index 074f33b..7431a58 100755 --- a/litex_boards/targets/xcu1525.py +++ b/litex_boards/targets/xcu1525.py @@ -76,8 +76,7 @@ class BaseSoC(SoCCore): pads = platform.request("ddram", ddram_channel), memtype = "DDR4", sys_clk_freq = sys_clk_freq, - iodelay_clk_freq = 500e6, - cmd_latency = 1) + iodelay_clk_freq = 500e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy, diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py index 0849a27..af15e74 100755 --- a/litex_boards/targets/zcu104.py +++ b/litex_boards/targets/zcu104.py @@ -71,8 +71,7 @@ class BaseSoC(SoCCore): self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), memtype = "DDR4", sys_clk_freq = sys_clk_freq, - iodelay_clk_freq = 500e6, - cmd_latency = 1) + iodelay_clk_freq = 500e6) self.add_csr("ddrphy") self.add_sdram("sdram", phy = self.ddrphy,