From c5d1a252c5a4767ce3e55f0ea954f429a745f1f9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 28 Aug 2024 15:53:53 +0200 Subject: [PATCH] targets: Fix build with --cpu-type=None on iCE40/Up5kSPRAM. --- litex_boards/targets/ice_v_wireless.py | 2 +- litex_boards/targets/icebreaker.py | 2 +- litex_boards/targets/icebreaker_bitsy.py | 2 +- litex_boards/targets/kosagi_fomu.py | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/litex_boards/targets/ice_v_wireless.py b/litex_boards/targets/ice_v_wireless.py index 67ef459..f8b6cd7 100755 --- a/litex_boards/targets/ice_v_wireless.py +++ b/litex_boards/targets/ice_v_wireless.py @@ -134,7 +134,7 @@ class BaseSoC(SoCCore): # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) ----------------------------------------------- self.spram = Up5kSPRAM(size=128 * KILOBYTE) - self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE)) + self.bus.add_slave("psram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE)) self.bus.add_region("sram", SoCRegion( origin = self.bus.regions["psram"].origin + 0 * KILOBYTE, size = 64 * KILOBYTE, diff --git a/litex_boards/targets/icebreaker.py b/litex_boards/targets/icebreaker.py index 2c93c12..22481a6 100755 --- a/litex_boards/targets/icebreaker.py +++ b/litex_boards/targets/icebreaker.py @@ -82,7 +82,7 @@ class BaseSoC(SoCCore): # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) ----------------------------------------------- self.spram = Up5kSPRAM(size=128 * KILOBYTE) - self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE)) + self.bus.add_slave("psram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE)) self.bus.add_region("sram", SoCRegion( origin = self.bus.regions["psram"].origin + 0 * KILOBYTE, size = 64 * KILOBYTE, diff --git a/litex_boards/targets/icebreaker_bitsy.py b/litex_boards/targets/icebreaker_bitsy.py index 9dce4bc..b554bf9 100755 --- a/litex_boards/targets/icebreaker_bitsy.py +++ b/litex_boards/targets/icebreaker_bitsy.py @@ -113,7 +113,7 @@ class BaseSoC(SoCCore): # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) ----------------------------------------------- self.spram = Up5kSPRAM(size=128 * KILOBYTE) - self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE)) + self.bus.add_slave("psram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE)) self.bus.add_region("sram", SoCRegion( origin = self.bus.regions["psram"].origin + 0 * KILOBYTE, size = 64 * KILOBYTE, diff --git a/litex_boards/targets/kosagi_fomu.py b/litex_boards/targets/kosagi_fomu.py index 4d8bb04..d4148ee 100755 --- a/litex_boards/targets/kosagi_fomu.py +++ b/litex_boards/targets/kosagi_fomu.py @@ -85,7 +85,7 @@ class BaseSoC(SoCCore): # 128KB SPRAM (used as 64kB SRAM / 64kB RAM) ----------------------------------------------- self.spram = Up5kSPRAM(size=128 * KILOBYTE) - self.bus.add_slave("psram", self.spram.bus, SoCRegion(size=128 * KILOBYTE)) + self.bus.add_slave("psram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=128 * KILOBYTE)) self.bus.add_region("sram", SoCRegion( origin = self.bus.regions["psram"].origin + 0 * KILOBYTE, size = 64 * KILOBYTE,