From c753bf7fc1a27a88cdb8ee9576d173827cb9fcf1 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 13 Jan 2023 11:47:52 +0100 Subject: [PATCH] ocp_tap_timecard: Fix GTPE2 location. --- litex_boards/targets/ocp_tap_timecard.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex_boards/targets/ocp_tap_timecard.py b/litex_boards/targets/ocp_tap_timecard.py index 0695de1..30dd33f 100755 --- a/litex_boards/targets/ocp_tap_timecard.py +++ b/litex_boards/targets/ocp_tap_timecard.py @@ -100,6 +100,8 @@ class BaseSoC(SoCCore): self.add_pcie(phy=self.pcie_phy, ndmas=1, address_width=64) # FIXME: Apply it to all targets (integrate it in LitePCIe?). platform.add_period_constraint(self.crg.cd_sys.clk, 1e9/sys_clk_freq) + platform.toolchain.pre_placement_commands.append("reset_property LOC [get_cells -hierarchical -filter {{NAME=~pcie_support/*gtp_channel.gtpe2_channel_i}}]") + platform.toolchain.pre_placement_commands.append("set_property LOC GTPE2_CHANNEL_X0Y5 [get_cells -hierarchical -filter {{NAME=~pcie_support/*gtp_channel.gtpe2_channel_i}}]") # ICAP (For FPGA reload over PCIe). from litex.soc.cores.icap import ICAP