From c836b571457758b94a04aa4fa66aa60c002a36f9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Jan 2022 15:18:26 +0100 Subject: [PATCH] titanium_ti60_f225_dev_kit: Add HyperRAM separator. --- litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py index 4cdd27e..8e6c002 100755 --- a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py +++ b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py @@ -66,6 +66,7 @@ class BaseSoC(SoCCore): from litespi.opcodes import SpiNorFlashOpCodes as Codes self.add_spi_flash(mode="1x", module=W25Q64JW(Codes.READ_1_1_1), with_master=True) + # HyperRAM --------------------------------------------------------------------------------- if with_hyperram: self.submodules.hyperram = HyperRAM(platform.request("hyperram"), latency=7) self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=32*1024*1024))