From c83e10d9f3730870067232a5a7741cf001ecca54 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Tue, 29 Oct 2019 11:54:14 -0400 Subject: [PATCH] official/platforms/versa_ecp5: add serdes refclk/sma Sync up with litex commit #ae9c25b74. --- litex_boards/official/platforms/versa_ecp5.py | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/litex_boards/official/platforms/versa_ecp5.py b/litex_boards/official/platforms/versa_ecp5.py index 7375895..ccf289e 100644 --- a/litex_boards/official/platforms/versa_ecp5.py +++ b/litex_boards/official/platforms/versa_ecp5.py @@ -121,6 +121,26 @@ _io = [ Subsignal("tx_n", Pins("W5")), Subsignal("perst", Pins("A6"), IOStandard("LVCMOS33")), ), + + ("refclk_en", 0, Pins("C12"), IOStandard("LVCMOS33")), + ("refclk_rst_n", 0, Pins("R1"), IOStandard("LVCMOS33")), + ("refclk", 0, + Subsignal("p", Pins("Y11")), + Subsignal("n", Pins("Y12")), + ), + ("refclk", 1, + Subsignal("p", Pins("Y19")), + Subsignal("n", Pins("W20")), + ), + + ("sma_tx", 0, + Subsignal("p", Pins("W8")), + Subsignal("n", Pins("W9")), + ), + ("sma_rx", 0, + Subsignal("p", Pins("Y7")), + Subsignal("n", Pins("Y8")), + ), ]