From c8603bebe4e5284073219ee4986c56909a67d146 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 4 Sep 2024 22:06:40 +0200 Subject: [PATCH] targets/hyperram: Switch Hyperram memory mode to rwx (required with VexiiRiscv). --- litex_boards/targets/antmicro_datacenter_ddr4_test_board.py | 2 +- litex_boards/targets/antmicro_lpddr4_test_board.py | 2 +- litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py | 2 +- litex_boards/targets/lattice_crosslink_nx_vip.py | 3 +-- litex_boards/targets/sipeed_tang_nano_4k.py | 2 +- litex_boards/targets/sipeed_tang_nano_9k.py | 2 +- litex_boards/targets/trenz_c10lprefkit.py | 2 +- litex_boards/targets/trenz_te0725.py | 2 +- 8 files changed, 8 insertions(+), 9 deletions(-) diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py index a4d341c..f357cea 100755 --- a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py +++ b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py @@ -118,7 +118,7 @@ class BaseSoC(SoCCore): # HyperRAM --------------------------------------------------------------------------------- if with_hyperram: self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq) - self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE)) + self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE, mode="rwx")) # SD Card ---------------------------------------------------------------------------------- if with_sdcard: diff --git a/litex_boards/targets/antmicro_lpddr4_test_board.py b/litex_boards/targets/antmicro_lpddr4_test_board.py index e130959..bc576e4 100755 --- a/litex_boards/targets/antmicro_lpddr4_test_board.py +++ b/litex_boards/targets/antmicro_lpddr4_test_board.py @@ -81,7 +81,7 @@ class BaseSoC(SoCCore): # HyperRAM --------------------------------------------------------------------------------- if with_hyperram: self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq) - self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE)) + self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE, mode="rwx")) # SD Card ---------------------------------------------------------------------------------- if with_sdcard: diff --git a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py index 9014faa..9f3c539 100755 --- a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py +++ b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py @@ -84,7 +84,7 @@ class BaseSoC(SoCCore): # HyperRAM Bus/Slave Interface. hyperram_bus = wishbone.Interface(data_width=32, address_width=32, addressing="word") - self.bus.add_slave(name="main_ram", slave=hyperram_bus, region=SoCRegion(origin=0x40000000, size=hyperram_size)) + self.bus.add_slave(name="main_ram", slave=hyperram_bus, region=SoCRegion(origin=0x40000000, size=hyperram_size, mode="rwx")) # HyperRAM L2 Cache. hyperram_cache = wishbone.Cache( diff --git a/litex_boards/targets/lattice_crosslink_nx_vip.py b/litex_boards/targets/lattice_crosslink_nx_vip.py index c7d6366..361aa34 100755 --- a/litex_boards/targets/lattice_crosslink_nx_vip.py +++ b/litex_boards/targets/lattice_crosslink_nx_vip.py @@ -87,8 +87,7 @@ class BaseSoC(SoCCore): size = 8 * MEGABYTE hr_pads = platform.request("hyperram", int(hyperram)) self.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq) - self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["sram"], - size=size)) + self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["sram"], size=size, mode="rwx")) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: diff --git a/litex_boards/targets/sipeed_tang_nano_4k.py b/litex_boards/targets/sipeed_tang_nano_4k.py index 6f728f0..afb9f6a 100755 --- a/litex_boards/targets/sipeed_tang_nano_4k.py +++ b/litex_boards/targets/sipeed_tang_nano_4k.py @@ -125,7 +125,7 @@ class BaseSoC(SoCCore): self.comb += platform.request("O_hpram_ck").eq(hyperram_pads.clk) self.comb += platform.request("O_hpram_ck_n").eq(~hyperram_pads.clk) self.hyperram = HyperRAM(hyperram_pads, sys_clk_freq=sys_clk_freq) - self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=8 * MEGABYTE)) + self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=8 * MEGABYTE, mode="rwx")) # Video ------------------------------------------------------------------------------------ if with_video_terminal: diff --git a/litex_boards/targets/sipeed_tang_nano_9k.py b/litex_boards/targets/sipeed_tang_nano_9k.py index 5a6b059..54503c7 100755 --- a/litex_boards/targets/sipeed_tang_nano_9k.py +++ b/litex_boards/targets/sipeed_tang_nano_9k.py @@ -112,7 +112,7 @@ class BaseSoC(SoCCore): os.system("mv hyperbus.py.txt hyperbus.py") from hyperbus import HyperRAM self.hyperram = HyperRAM(hyperram_pads) - self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["main_ram"], size=4 * MEGABYTE)) + self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=self.mem_map["main_ram"], size=4 * MEGABYTE, mode="rwx")) # Video ------------------------------------------------------------------------------------ if with_video_terminal: diff --git a/litex_boards/targets/trenz_c10lprefkit.py b/litex_boards/targets/trenz_c10lprefkit.py index 88ec800..4800540 100755 --- a/litex_boards/targets/trenz_c10lprefkit.py +++ b/litex_boards/targets/trenz_c10lprefkit.py @@ -73,7 +73,7 @@ class BaseSoC(SoCCore): # HyperRam --------------------------------------------------------------------------------- self.hyperram = HyperRAM(platform.request("hyperram"), sys_clk_freq=sys_clk_freq) - self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE)) + self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8 * MEGABYTE, mode="rwx")) # SDR SDRAM -------------------------------------------------------------------------------- if not self.integrated_main_ram_size: diff --git a/litex_boards/targets/trenz_te0725.py b/litex_boards/targets/trenz_te0725.py index e254c83..19d400d 100755 --- a/litex_boards/targets/trenz_te0725.py +++ b/litex_boards/targets/trenz_te0725.py @@ -48,7 +48,7 @@ class BaseSoC(SoCCore): size = int((64 * MEGABYTE) / 8) hr_pads = platform.request("hyperram", 0) self.hyperram = HyperRAM(hr_pads, sys_clk_freq=sys_clk_freq) - self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=size)) + self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=size, mode="rwx")) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: