From c87412b09839f5ef49dfe8f9a9041ead3dfecd83 Mon Sep 17 00:00:00 2001
From: Tom Keddie <git@bronwenandtom.com>
Date: Fri, 7 Jun 2019 06:29:07 -0700
Subject: [PATCH] Review feedback - rename dvt to pvt - remove serial from both
 pvt and hacker - remove NC spi wp and hold pins from hacker - remove
 spiflash4x as pins are NC Added links to schematic/cad data

---
 litex/boards/platforms/fomu_evt.py    |  3 ++
 litex/boards/platforms/fomu_hacker.py | 16 ++----
 litex/boards/platforms/fomu_pvt.py    | 76 +++++++++++++++++++++++++++
 3 files changed, 83 insertions(+), 12 deletions(-)
 create mode 100644 litex/boards/platforms/fomu_pvt.py

diff --git a/litex/boards/platforms/fomu_evt.py b/litex/boards/platforms/fomu_evt.py
index 35a5cd5..f05efd2 100644
--- a/litex/boards/platforms/fomu_evt.py
+++ b/litex/boards/platforms/fomu_evt.py
@@ -1,3 +1,6 @@
+# fomu evt board from from crowd funding
+# design files at https://github.com/im-tomu/fomu-hardware/tree/evt/hardware/pcb
+#
 from litex.build.generic_platform import *
 from litex.build.lattice import LatticePlatform
 from litex.build.lattice.programmer import IceStormProgrammer
diff --git a/litex/boards/platforms/fomu_hacker.py b/litex/boards/platforms/fomu_hacker.py
index dff3e65..2f64152 100644
--- a/litex/boards/platforms/fomu_hacker.py
+++ b/litex/boards/platforms/fomu_hacker.py
@@ -1,14 +1,13 @@
+# fomu hacker board
+# schematic at https://github.com/im-tomu/fomu-hardware/tree/master/hacker/releases/v0.0-19-g154fecc
+#
+
 from litex.build.generic_platform import *
 from litex.build.lattice import LatticePlatform
 from litex.build.lattice.programmer import IceStormProgrammer
 
 
 _io = [
-    ("serial", 0,
-        Subsignal("rx", Pins("C3")),
-        Subsignal("tx", Pins("B3"), Misc("PULLUP")),
-        IOStandard("LVCMOS33")
-    ),
     ("rgb_led", 0,
         Subsignal("r", Pins("C5")),
         Subsignal("g", Pins("B5")),
@@ -41,13 +40,6 @@ _io = [
         Subsignal("clk", Pins("D1"), IOStandard("LVCMOS33")),
         Subsignal("mosi", Pins("F1"), IOStandard("LVCMOS33")),
         Subsignal("miso", Pins("E1"), IOStandard("LVCMOS33")),
-        Subsignal("wp",   Pins("A1"), IOStandard("LVCMOS33")),
-        Subsignal("hold", Pins("B1"), IOStandard("LVCMOS33")),
-    ),
-    ("spiflash4x", 0,
-        Subsignal("cs_n", Pins("C1"), IOStandard("LVCMOS33")),
-        Subsignal("clk",  Pins("D1"), IOStandard("LVCMOS33")),
-        Subsignal("dq",   Pins("E1 F1 A1 B1"), IOStandard("LVCMOS33")),
     ),
 ]
 
diff --git a/litex/boards/platforms/fomu_pvt.py b/litex/boards/platforms/fomu_pvt.py
new file mode 100644
index 0000000..4c6c2b5
--- /dev/null
+++ b/litex/boards/platforms/fomu_pvt.py
@@ -0,0 +1,76 @@
+# fomu pvt board from crowd funding
+# design files at https://github.com/im-tomu/fomu-hardware/tree/pvt/hardware/pcb
+#
+
+from litex.build.generic_platform import *
+from litex.build.lattice import LatticePlatform
+from litex.build.lattice.programmer import IceStormProgrammer
+
+
+_io = [
+    ("rgb_led", 0,
+        Subsignal("r", Pins("C5")),
+        Subsignal("g", Pins("B5")),
+        Subsignal("b", Pins("A5")),
+        IOStandard("LVCMOS33")
+    ),
+    # alias blue led
+    ("user_led_n",    0, Pins("A5"), IOStandard("LVCMOS33")),
+
+    ("usb", 0,
+        Subsignal("d_p", Pins("A1")),
+        Subsignal("d_n", Pins("A2")),
+        Subsignal("pullup", Pins("A4")),
+        IOStandard("LVCMOS33")
+    ),
+
+    ("clk48", 0, Pins("F4"), IOStandard("LVCMOS33")),
+
+    # Adesto AT25SF161 - 16-Mbit - 2 megabyte
+    # Supports SPI Modes 0 and 3
+    # Supports Dual and Quad Output Read
+    #
+    ("spiflash", 0,
+        Subsignal("cs_n", Pins("C1"), IOStandard("LVCMOS33")),
+        Subsignal("clk", Pins("D1"), IOStandard("LVCMOS33")),
+        Subsignal("mosi", Pins("F1"), IOStandard("LVCMOS33")),
+        Subsignal("miso", Pins("E1"), IOStandard("LVCMOS33")),
+        Subsignal("wp",   Pins("F2"), IOStandard("LVCMOS33")),
+        Subsignal("hold", Pins("B1"), IOStandard("LVCMOS33")),
+    ),
+    ("spiflash4x", 0,
+        Subsignal("cs_n", Pins("C1"), IOStandard("LVCMOS33")),
+        Subsignal("clk",  Pins("D1"), IOStandard("LVCMOS33")),
+        Subsignal("dq",   Pins("E1 F1 F2 B1"), IOStandard("LVCMOS33")),
+    ),
+]
+
+_connectors = [
+    # Pins
+    # Pin 1
+    # Pin 2
+    # Pin 3
+    # Pin 4
+    ("touch_pins", "E4 D5 E5 F5"),
+]
+
+class Platform(LatticePlatform):
+    default_clk_name = "clk48"
+    default_clk_period = 20.833
+
+    gateware_size = 0x20000
+
+    # FIXME: Create a "spi flash module" object in the same way we have SDRAM
+    spiflash_model = "n25q32"
+    spiflash_read_dummy_bits = 8
+    spiflash_clock_div = 2
+    spiflash_total_size = int((16/8)*1024*1024) # 16Mbit, 1megabytes
+    spiflash_page_size = 256
+    spiflash_sector_size = 0x10000
+
+    def __init__(self):
+        LatticePlatform.__init__(
+            self, "ice40-up5k-uwg30", _io, _connectors, toolchain="icestorm")
+
+    def create_programmer(self):
+        return IceStormProgrammer()