From c90950e3196d208dd688a73ba85946686948fbe8 Mon Sep 17 00:00:00 2001 From: DurandA Date: Fri, 9 Aug 2019 11:57:39 +0200 Subject: [PATCH] Default to 60 Mhz system clock on ECP5 Evaluation Board Exact PLL clock can be derived from U1 12 Mhz or X5 50 Mhz clock. --- litex_boards/community/targets/ecp5_evn.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/community/targets/ecp5_evn.py b/litex_boards/community/targets/ecp5_evn.py index bd365b4..3b1a766 100755 --- a/litex_boards/community/targets/ecp5_evn.py +++ b/litex_boards/community/targets/ecp5_evn.py @@ -62,8 +62,8 @@ def main(): help='gateware toolchain to use, diamond (default) or trellis') builder_args(parser) soc_core_args(parser) - parser.add_argument("--sys-clk-freq", default=50e6, - help="system clock frequency (default=50MHz)") + parser.add_argument("--sys-clk-freq", default=60e6, + help="system clock frequency (default=60MHz)") parser.add_argument("--x5-clk-freq", type=int, help="use X5 oscillator as system clock at the specified frequency") args = parser.parse_args()