diff --git a/litex_boards/targets/rcs_arctic_tern_bmc_card.py b/litex_boards/targets/rcs_arctic_tern_bmc_card.py
index f1b2006..6b634b4 100755
--- a/litex_boards/targets/rcs_arctic_tern_bmc_card.py
+++ b/litex_boards/targets/rcs_arctic_tern_bmc_card.py
@@ -11,8 +11,6 @@
 from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
-from litex_boards.platforms import versa_ecp5
-
 from litex.build.lattice.trellis import trellis_args, trellis_argdict
 
 from litex_boards.platforms import rcs_arctic_tern_bmc_card
diff --git a/litex_boards/targets/sipeed_tang_nano_9k.py b/litex_boards/targets/sipeed_tang_nano_9k.py
index 5921f4d..bd19ed6 100755
--- a/litex_boards/targets/sipeed_tang_nano_9k.py
+++ b/litex_boards/targets/sipeed_tang_nano_9k.py
@@ -8,7 +8,7 @@
 
 from migen import *
 
-from litex_boards.platforms import tang_nano_9k
+from litex_boards.platforms import sipeed_tang_nano_9k
 
 from litex.soc.cores.clock.gowin_gw1n import GW1NPLL
 from litex.soc.integration.soc_core import *
@@ -46,7 +46,7 @@ class _CRG(Module):
 class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=int(27e6), bios_flash_offset=0x0,
                  with_led_chaser=True, **kwargs):
-        platform = tang_nano_9k.Platform()
+        platform = sipeed_tang_nano_9k.Platform()
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)