diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py index e6342c1..9e869a8 100755 --- a/litex_boards/targets/ac701.py +++ b/litex_boards/targets/ac701.py @@ -11,7 +11,6 @@ from migen import * from litex_boards.platforms import ac701 from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py index 08d5dde..0338607 100755 --- a/litex_boards/targets/c10lprefkit.py +++ b/litex_boards/targets/c10lprefkit.py @@ -101,7 +101,7 @@ class BaseSoC(SoCSDRAM): # HyperRam --------------------------------------------------------------------------------- self.submodules.hyperram = HyperRAM(platform.request("hyperram")) - self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus) + self.add_wb_slave(self.mem_map["hyperram"], self.hyperram.bus) self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024) # SDR SDRAM -------------------------------------------------------------------------------- diff --git a/litex_boards/targets/de10lite.py b/litex_boards/targets/de10lite.py index e14b23f..5293c9e 100755 --- a/litex_boards/targets/de10lite.py +++ b/litex_boards/targets/de10lite.py @@ -12,7 +12,6 @@ from litex_boards.platforms import de10lite from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * -from litex.soc.integration.soc_core import mem_decoder from litedram.modules import IS42S16320 from litedram.phy import GENSDRPHY @@ -111,7 +110,7 @@ class VGASoC(BaseSoC): # create VGA terminal self.submodules.terminal = terminal = Terminal() - self.add_wb_slave(mem_decoder(self.mem_map["terminal"]), self.terminal.bus) + self.add_wb_slave(self.mem_map["terminal"], self.terminal.bus) self.add_memory_region("terminal", self.mem_map["terminal"], 0x10000) # connect VGA pins