From c9816f2bc1d3230f1e412505433cd626cc9eb392 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 3 Jan 2022 17:15:27 +0100 Subject: [PATCH] snicker_doodle: Add z7-10/z7-20 variants support. --- litex_boards/platforms/krtkl_snickerdoodle.py | 8 ++++++-- litex_boards/targets/krtkl_snickerdoodle.py | 6 ++++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/litex_boards/platforms/krtkl_snickerdoodle.py b/litex_boards/platforms/krtkl_snickerdoodle.py index b182a12..cf8793d 100644 --- a/litex_boards/platforms/krtkl_snickerdoodle.py +++ b/litex_boards/platforms/krtkl_snickerdoodle.py @@ -70,8 +70,12 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_freq = 100e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io, _connectors, toolchain="vivado") + def __init__(self, variant="z7-10"): + device = { + "z7-10": "xc7z010-clg400-1", + "z7-20": "xc7z020-clg400-3" + }[variant] + XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado") self.default_clk_period = 1e9 / self.default_clk_freq self.toolchain.bitstream_commands = [ "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]" diff --git a/litex_boards/targets/krtkl_snickerdoodle.py b/litex_boards/targets/krtkl_snickerdoodle.py index 0479636..3626e5f 100755 --- a/litex_boards/targets/krtkl_snickerdoodle.py +++ b/litex_boards/targets/krtkl_snickerdoodle.py @@ -63,12 +63,12 @@ class _CRG(Module): class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, + def __init__(self, variant="z7-10", sys_clk_freq=int(100e6), with_led_chaser=True, ext_clk_freq = None, xci_file = None, **kwargs): - platform = snickerdoodle.Platform() + platform = snickerdoodle.Platform(variant=variant) if ext_clk_freq: platform.default_clk_freq = ext_clk_freq @@ -116,6 +116,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Snickerdoodle") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--variant", default="z7-10", help="Board variant: z7-10 (default) or z7-20") parser.add_argument("--ext-clk-freq", default=10e6, type=float, help="External Clock Frequency") parser.add_argument("--sys-clk-freq", default=100e6, type=float, help="System clock frequency") parser.add_argument("--xci-file", help="XCI file for PS7 configuration") @@ -126,6 +127,7 @@ def main(): args = parser.parse_args() soc = BaseSoC( + variant = args.variant, sys_clk_freq = args.sys_clk_freq, ext_clk_freq = args.ext_clk_freq, xci_file = args.xci_file,