diff --git a/litex_boards/targets/machdyne_vanille.py b/litex_boards/targets/machdyne_vanille.py
index 221d73a..647ae19 100755
--- a/litex_boards/targets/machdyne_vanille.py
+++ b/litex_boards/targets/machdyne_vanille.py
@@ -111,6 +111,9 @@ class BaseSoC(SoCCore):
         self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate)
 
         # SoCCore ----------------------------------------------------------------------------------
+
+        kwargs['uart_name'] = "stub"
+
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Vanille", **kwargs)
 
         # DRAM -------------------------------------------------------------------------------------