From cb43cdf6f9dd2d62ba518d7a2cd16a65cc770620 Mon Sep 17 00:00:00 2001 From: inc <87362+inc@users.noreply.github.com> Date: Sat, 22 Jun 2024 12:13:30 +0200 Subject: [PATCH] targets/machdyne_vanille: set uart_name to stub --- litex_boards/targets/machdyne_vanille.py | 3 +++ 1 file changed, 3 insertions(+) diff --git a/litex_boards/targets/machdyne_vanille.py b/litex_boards/targets/machdyne_vanille.py index 221d73a..647ae19 100755 --- a/litex_boards/targets/machdyne_vanille.py +++ b/litex_boards/targets/machdyne_vanille.py @@ -111,6 +111,9 @@ class BaseSoC(SoCCore): self.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate) # SoCCore ---------------------------------------------------------------------------------- + + kwargs['uart_name'] = "stub" + SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Vanille", **kwargs) # DRAM -------------------------------------------------------------------------------------