From cc78574297eb232ace752c91d0e809c9dc26dee4 Mon Sep 17 00:00:00 2001 From: DerFetzer Date: Wed, 2 Sep 2020 22:04:23 +0200 Subject: [PATCH] targets/colorlight_5a_75x: fix rx_data pin order for Ethernet PHY 0 --- litex_boards/platforms/colorlight_5a_75e.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/platforms/colorlight_5a_75e.py b/litex_boards/platforms/colorlight_5a_75e.py index d85bdc9..96b8f87 100644 --- a/litex_boards/platforms/colorlight_5a_75e.py +++ b/litex_boards/platforms/colorlight_5a_75e.py @@ -156,7 +156,7 @@ _io_v6_0 = [ Subsignal("mdio", Pins("T4")), Subsignal("mdc", Pins("R5")), Subsignal("rx_ctl", Pins("J2")), - Subsignal("rx_data", Pins("J3 K2 K1 K3")), + Subsignal("rx_data", Pins("K2 J3 K1 K3")), Subsignal("tx_ctl", Pins("L2")), Subsignal("tx_data", Pins("M2 M1 P1 R1")), IOStandard("LVCMOS33")