diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
index 637a8bc..fae2f1a 100755
--- a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
+++ b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py
@@ -15,6 +15,7 @@ from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
+from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
@@ -47,11 +48,6 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    mem_map = {
-        "hyperram": 0x20000000,
-    }
-    mem_map.update(SoCCore.mem_map)
-
     def __init__(self, *, sys_clk_freq=int(100e6), iodelay_clk_freq=200e6,
             with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
             with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False,
@@ -86,7 +82,7 @@ class BaseSoC(SoCCore):
         # HyperRAM ---------------------------------------------------------------------------------
         if with_hyperram:
             self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
-            self.register_mem("hyperram", self.mem_map["hyperram"], self.hyperram.bus, 8*1024*1024)
+            self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024))
 
         # SD Card ----------------------------------------------------------------------------------
         if with_sdcard:
diff --git a/litex_boards/targets/antmicro_lpddr4_test_board.py b/litex_boards/targets/antmicro_lpddr4_test_board.py
index 4e370fe..7155666 100755
--- a/litex_boards/targets/antmicro_lpddr4_test_board.py
+++ b/litex_boards/targets/antmicro_lpddr4_test_board.py
@@ -15,6 +15,7 @@ from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
+from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
@@ -47,11 +48,6 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    mem_map = {
-        "hyperram": 0x20000000,
-    }
-    mem_map.update(SoCCore.mem_map)
-
     def __init__(self, *, sys_clk_freq=int(50e6), iodelay_clk_freq=200e6,
             with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False,
             with_hyperram=False, with_sdcard=False, with_jtagbone=True, with_uartbone=False,
@@ -83,7 +79,7 @@ class BaseSoC(SoCCore):
         # HyperRAM ---------------------------------------------------------------------------------
         if with_hyperram:
             self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
-            self.register_mem("hyperram", self.mem_map["hyperram"], self.hyperram.bus, 8*1024*1024)
+            self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=8*1024*1024))
 
         # SD Card ----------------------------------------------------------------------------------
         if with_sdcard:
diff --git a/litex_boards/targets/lattice_crosslink_nx_vip.py b/litex_boards/targets/lattice_crosslink_nx_vip.py
index 557c1d9..8408ea8 100755
--- a/litex_boards/targets/lattice_crosslink_nx_vip.py
+++ b/litex_boards/targets/lattice_crosslink_nx_vip.py
@@ -27,6 +27,7 @@ from litex.build.generic_platform import *
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
+from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
@@ -89,13 +90,13 @@ class BaseSoC(SoCCore):
             # 128KB LRAM (used as SRAM) ------------------------------------------------------------
             size = 128*kB
             self.submodules.spram = NXLRAM(32, size)
-            self.register_mem("sram", self.mem_map["sram"], self.spram.bus, size)
+            self.bus.add_slave("sram", slave=self.spram.bus, region=SoCRegion(size=size))
         else:
             # Use HyperRAM generic PHY as SRAM -----------------------------------------------------
             size = 8*1024*kB
             hr_pads = platform.request("hyperram", int(hyperram))
             self.submodules.hyperram = HyperRAM(hr_pads)
-            self.register_mem("sram", self.mem_map["sram"], self.hyperram.bus, size)
+            self.bus.add_slave("sram", slave=self.hyperram.bus, region=SoCRegion(size=size))
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
diff --git a/litex_boards/targets/trenz_te0725.py b/litex_boards/targets/trenz_te0725.py
index 5330eca..60dbd8e 100755
--- a/litex_boards/targets/trenz_te0725.py
+++ b/litex_boards/targets/trenz_te0725.py
@@ -37,13 +37,6 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    mem_map = {
-        **SoCCore.mem_map,
-        **{
-            "hyperram": 0x20000000,
-        }
-    }
-
     def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True, **kwargs):
         platform = trenz_te0725.Platform()
 
@@ -60,7 +53,7 @@ class BaseSoC(SoCCore):
         size = int((64*1024*1024) / 8)
         hr_pads = platform.request("hyperram", 0)
         self.submodules.hyperram = HyperRAM(hr_pads)
-        self.register_mem("hyperram", self.mem_map["hyperram"], self.hyperram.bus, size)
+        self.bus.add_slave("hyperram", slave=self.hyperram.bus, region=SoCRegion(origin=0x20000000, size=size))
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser: