From 90de99eb462fe7a25586cd18b050296cc823c44b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C4=99drzej=20Boczar?= Date: Tue, 10 Mar 2020 14:38:15 +0100 Subject: [PATCH] platforms/mercury_xu5: fix sdram timing issues --- litex_boards/platforms/mercury_xu5.py | 97 +++++++-------------------- litex_boards/targets/mercury_xu5.py | 16 ++--- 2 files changed, 32 insertions(+), 81 deletions(-) diff --git a/litex_boards/platforms/mercury_xu5.py b/litex_boards/platforms/mercury_xu5.py index 50e5591..487b3f1 100644 --- a/litex_boards/platforms/mercury_xu5.py +++ b/litex_boards/platforms/mercury_xu5.py @@ -36,89 +36,40 @@ _io = [ IOStandard("LVCMOS33"), ), - ("ddram", 0, # TODO: remove Misc with default settings + ("i2c", 0, + Subsignal("scl", Pins("D12")), + Subsignal("sda", Pins("C12")), + IOStandard("LVCMOS18") + ), + + ("ddram", 0, Subsignal("a", Pins( "AC4 AC3 AB4 AB3 AB2 AC2 AB1 AC1", - "AB5 AG4 AH4 AG3 AH3 AE3"), IOStandard("SSTL12_DCI"), - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - Misc("DATA_RATE=DDR"), - ), - Subsignal("we_n", Pins("AF3"), IOStandard("SSTL12_DCI"), # A14 - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - Misc("DATA_RATE=DDR"), - ), - Subsignal("cas_n", Pins("AE2"), IOStandard("SSTL12_DCI"), # A15 - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - Misc("DATA_RATE=DDR"), - ), - Subsignal("ras_n", Pins("AF2"), IOStandard("SSTL12_DCI"), # A16 - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - Misc("DATA_RATE=DDR"), - ), - Subsignal("ba", Pins("AH1 AF1"), IOStandard("SSTL12_DCI"), - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - Misc("DATA_RATE=DDR"), - ), - # Subsignal("bg", Pins("AG1 AD9"), IOStandard("SSTL12_DCI"), - Subsignal("bg", Pins("AG1"), IOStandard("SSTL12_DCI"), - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - Misc("DATA_RATE=DDR"), - ), - Subsignal("cs_n", Pins("AH9"), IOStandard("SSTL12_DCI"), - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - Misc("DATA_RATE=SDR"), - ), - Subsignal("act_n", Pins("AH2"), IOStandard("SSTL12_DCI"), - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - Misc("DATA_RATE=DDR"), - ), - Subsignal("dm", Pins("AC9 AG9"), IOStandard("POD12_DCI"), - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - # Misc("EQUALIZATION=EQ_LEVEL2"), - Misc("DATA_RATE=DDR"), - ), + "AB5 AG4 AH4 AG3 AH3 AE3"), IOStandard("SSTL12_DCI")), + Subsignal("we_n", Pins("AF3"), IOStandard("SSTL12_DCI")), # A14 + Subsignal("cas_n", Pins("AE2"), IOStandard("SSTL12_DCI")), # A15 + Subsignal("ras_n", Pins("AF2"), IOStandard("SSTL12_DCI")), # A16 + Subsignal("ba", Pins("AH1 AF1"), IOStandard("SSTL12_DCI")), + Subsignal("bg", Pins("AG1"), IOStandard("SSTL12_DCI")), + Subsignal("cs_n", Pins("AH9"), IOStandard("SSTL12_DCI")), + Subsignal("act_n", Pins("AH2"), IOStandard("SSTL12_DCI")), + Subsignal("dm", Pins("AC9 AG9"), IOStandard("POD12_DCI")), Subsignal("dq", Pins( "AB6 AC6 AE9 AE8 AB8 AC8 AB7 AC7", "AE5 AF5 AF8 AG8 AH8 AH7 AF7 AF6"), IOStandard("POD12_DCI"), Misc("PRE_EMPHASIS=RDRV_240"), - Misc("EQUALIZATION=EQ_LEVEL2"), - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - Misc("DATA_RATE=DDR"), - Misc("ODT=RTT_40"), - ), + Misc("EQUALIZATION=EQ_LEVEL2")), Subsignal("dqs_p", Pins("AD7 AG6"), IOStandard("DIFF_POD12_DCI"), Misc("PRE_EMPHASIS=RDRV_240"), - Misc("EQUALIZATION=EQ_LEVEL2"), - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - Misc("DATA_RATE=DDR"), - Misc("ODT=RTT_40"), - ), + Misc("EQUALIZATION=EQ_LEVEL2")), Subsignal("dqs_n", Pins("AE7 AG5"), IOStandard("DIFF_POD12_DCI"), Misc("PRE_EMPHASIS=RDRV_240"), - Misc("EQUALIZATION=EQ_LEVEL2"), - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - Misc("DATA_RATE=DDR"), - Misc("ODT=RTT_40"), - ), - Subsignal("clk_p", Pins("AD2"), IOStandard("DIFF_SSTL12_DCI"), - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - Misc("DATA_RATE=DDR"), - ), - Subsignal("clk_n", Pins("AD1"), IOStandard("DIFF_SSTL12_DCI"), - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - Misc("DATA_RATE=DDR"), - ), - Subsignal("cke", Pins("AH6"), IOStandard("SSTL12_DCI"), - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - Misc("DATA_RATE=DDR"), - ), - Subsignal("odt", Pins("AE4"), IOStandard("SSTL12_DCI"), - Misc("OUTPUT_IMPEDANCE=RDRV_40_40"), - Misc("DATA_RATE=DDR"), - ), - Subsignal("reset_n", Pins("G4"), IOStandard("LVCMOS18"), - Misc("DRIVE=8"), - ), + Misc("EQUALIZATION=EQ_LEVEL2")), + Subsignal("clk_p", Pins("AD2"), IOStandard("DIFF_SSTL12_DCI")), + Subsignal("clk_n", Pins("AD1"), IOStandard("DIFF_SSTL12_DCI")), + Subsignal("cke", Pins("AH6"), IOStandard("SSTL12_DCI")), + Subsignal("odt", Pins("AE4"), IOStandard("SSTL12_DCI")), + Subsignal("reset_n", Pins("G4"), IOStandard("LVCMOS18")), Misc("SLEW=FAST"), ), ] diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py index f542dde..b447c2d 100755 --- a/litex_boards/targets/mercury_xu5.py +++ b/litex_boards/targets/mercury_xu5.py @@ -24,14 +24,14 @@ class _CRG(Module): self.clock_domains.cd_sys = ClockDomain() self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) - self.clock_domains.cd_clk400 = ClockDomain() + self.clock_domains.cd_clk200 = ClockDomain() self.clock_domains.cd_ic = ClockDomain() self.submodules.pll = pll = USMMCM(speedgrade=-1) pll.register_clkin(platform.request("clk100"), 100e6) pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False) - pll.create_clkout(self.cd_clk400, 400e6, with_reset=False) + pll.create_clkout(self.cd_clk200, 200e6, with_reset=False) self.specials += [ Instance("BUFGCE_DIV", name="main_bufgce_div", @@ -39,12 +39,12 @@ class _CRG(Module): i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys.clk), Instance("BUFGCE", name="main_bufgce", i_CE=1, i_I=self.cd_pll4x.clk, o_O=self.cd_sys4x.clk), - AsyncResetSynchronizer(self.cd_clk400, ~pll.locked), + AsyncResetSynchronizer(self.cd_clk200, ~pll.locked), ] ic_reset_counter = Signal(max=64, reset=63) ic_reset = Signal(reset=1) - self.sync.clk400 += \ + self.sync.clk200 += \ If(ic_reset_counter != 0, ic_reset_counter.eq(ic_reset_counter - 1) ).Else( @@ -65,7 +65,7 @@ class _CRG(Module): ] self.specials += [ Instance("IDELAYCTRL", p_SIM_DEVICE="ULTRASCALE", - i_REFCLK=ClockSignal("clk400"), i_RST=ic_reset, + i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset, o_RDY=ic_rdy), AsyncResetSynchronizer(self.cd_ic, ic_reset) ] @@ -73,7 +73,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(100e6), **kwargs): + def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = mercury_xu5.Platform() # SoCSDRAM --------------------------------------------------------------------------------- @@ -87,8 +87,8 @@ class BaseSoC(SoCSDRAM): self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), memtype = "DDR4", sim_device = "ULTRASCALE_PLUS", - iodelay_clk_freq = 400e6, - cmd_latency = 1, + iodelay_clk_freq = 200e6, + cmd_latency = 0, sys_clk_freq = sys_clk_freq) self.add_csr("ddrphy") self.add_constant("USDDRPHY", None)