From ceaaf67dfd89299b14b786e2597847e7a1874c32 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 5 Nov 2021 08:01:54 +0100 Subject: [PATCH] Add initial Fairwaves XTRX support (SoC with JTAG-UART and PCIe Gen2 X1). --- litex_boards/__init__.py | 1 + litex_boards/platforms/fairwaves_xtrx.py | 53 ++++++++++ litex_boards/targets/fairwaves_xtrx.py | 122 +++++++++++++++++++++++ 3 files changed, 176 insertions(+) create mode 100644 litex_boards/platforms/fairwaves_xtrx.py create mode 100755 litex_boards/targets/fairwaves_xtrx.py diff --git a/litex_boards/__init__.py b/litex_boards/__init__.py index 57d82fe..6a7f464 100644 --- a/litex_boards/__init__.py +++ b/litex_boards/__init__.py @@ -14,6 +14,7 @@ vendors = [ "digilent", "enclustra", "gsd", + "fairwaves", "hackaday", "kosagi", "lattice", diff --git a/litex_boards/platforms/fairwaves_xtrx.py b/litex_boards/platforms/fairwaves_xtrx.py new file mode 100644 index 0000000..0a1a2be --- /dev/null +++ b/litex_boards/platforms/fairwaves_xtrx.py @@ -0,0 +1,53 @@ +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2021 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +# https://www.crowdsupply.com/fairwaves/xtrx + +from litex.build.generic_platform import * +from litex.build.xilinx import XilinxPlatform +from litex.build.openocd import OpenOCD + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # Leds. + ("user_led", 0, Pins("N18"), IOStandard("LVCMOS25")), + + # PCIe. + ("pcie_x1", 0, + Subsignal("rst_n", Pins("T3"), IOStandard("LVCMOS25"), Misc("PULLUP=TRUE")), + Subsignal("clk_p", Pins("B8")), + Subsignal("clk_n", Pins("A8")), + Subsignal("rx_p", Pins("B10")), + Subsignal("rx_n", Pins("A10")), + Subsignal("tx_p", Pins("B6")), + Subsignal("tx_n", Pins("A6")), + ), +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(XilinxPlatform): + default_clk_name = "clk60" + default_clk_period = 1e9/60e6 + + def __init__(self): + XilinxPlatform.__init__(self, "xc7a50tcpg236-2", _io, toolchain="vivado") + + self.toolchain.bitstream_commands = [ + "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", + "set_property BITSTREAM.CONFIG.CONFIGRATE 16 [current_design]", + "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]" + ] + self.toolchain.additional_commands = \ + ["write_cfgmem -force -format bin -interface spix4 -size 16 " + "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] + + def create_programmer(self): + return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a50t.bit") + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/targets/fairwaves_xtrx.py b/litex_boards/targets/fairwaves_xtrx.py new file mode 100755 index 0000000..6895720 --- /dev/null +++ b/litex_boards/targets/fairwaves_xtrx.py @@ -0,0 +1,122 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2021 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +# Build/Use ---------------------------------------------------------------------------------------- +# Build/Flash bitstream: +# ./fairwaves_xtrx.py --uart-name=crossover --with-pcie --build --driver --flash +# +#.Build the kernel and load it: +# cd build//driver/kernel +# make +# sudo ./init.sh +# +# Test userspace utilities: +# cd build//driver/user +# make +# ./litepcie_util info +# ./litepcie_util scratch_test +# ./litepcie_util dma_test +# ./litepcie_util uart_test + +import os +import argparse +import sys + +from migen import * + +from litex_boards.platforms import fairwaves_xtrx + +from litex.soc.interconnect.csr import * +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * + +from litex.soc.cores.led import LedChaser +from litex.soc.cores.clock import * + +from litepcie.phy.s7pciephy import S7PCIEPHY +from litepcie.software import generate_litepcie_software + +# CRG ---------------------------------------------------------------------------------------------- + +class CRG(Module): + def __init__(self, platform, sys_clk_freq, with_pcie=False): + assert sys_clk_freq == int(125e6) + self.clock_domains.cd_sys = ClockDomain() + + # # # + + self.comb += [ + self.cd_sys.clk.eq(ClockSignal("pcie")), + self.cd_sys.rst.eq(ResetSignal("pcie")), + + ] + +# BaseSoC ----------------------------------------------------------------------------------------- + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(125e6), with_pcie=False, with_led_chaser=True, **kwargs): + assert with_pcie + platform = fairwaves_xtrx.Platform() + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on Fairwaves XTRX", + ident_version = True, + **kwargs) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = CRG(platform, sys_clk_freq) + + # PCIe ------------------------------------------------------------------------------------- + if with_pcie: + self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), + data_width = 64, + bar0_size = 0x20000) + self.add_pcie(phy=self.pcie_phy, ndmas=1) + + # Leds ------------------------------------------------------------------------------------- + if with_led_chaser: + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + +# Build -------------------------------------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on Fairwaves XTRX") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--flash", action="store_true", help="Flash bitstream") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") + builder_args(parser) + soc_core_args(parser) + args = parser.parse_args() + + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_pcie = args.with_pcie, + **soc_core_argdict(args) + ) + builder = Builder(soc, **builder_argdict(args)) + builder.build(run=args.build) + + if args.driver: + generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit")) + + if args.flash: + prog = soc.platform.create_programmer() + prog.flash(0, os.path.join(builder.gateware_dir, soc.build_name + ".bin")) + +if __name__ == "__main__": + main()