From cf416d0d66e4b2e5ab867973dd24aa22e327f976 Mon Sep 17 00:00:00 2001 From: Vadzim Dambrouski Date: Sat, 1 Oct 2022 10:49:01 +0300 Subject: [PATCH] stlv7325: Adjust DDR3 pins to match reference design --- litex_boards/platforms/aliexpress_stlv7325.py | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/litex_boards/platforms/aliexpress_stlv7325.py b/litex_boards/platforms/aliexpress_stlv7325.py index cc69565..816468b 100644 --- a/litex_boards/platforms/aliexpress_stlv7325.py +++ b/litex_boards/platforms/aliexpress_stlv7325.py @@ -59,7 +59,7 @@ _io = [ ("ddram", 0, Subsignal("a", Pins( "AB7 AD11 AA8 AF10 AC7 AE11 AC8 AD8", - "AC13 AF12 AF9 AD10 AE13 AF7 AB12"), + "AC13 AF12 AF9 AD10 AE13 AF7 AB12 AC12"), IOStandard("SSTL15")), Subsignal("ba", Pins("AE8 AA7 AF13"), IOStandard("SSTL15")), Subsignal("ras_n", Pins("Y7"), IOStandard("SSTL15")), @@ -80,13 +80,15 @@ _io = [ " AD4 AD1 AF2 AE2 AE6 AE5 AF3 AE3"), IOStandard("SSTL15_T_DCI")), Subsignal("dqs_p", Pins("AE18 Y15 AD20 W18 W6 AB1 AA5 AF5"), - IOStandard("DIFF_SSTL15")), + IOStandard("DIFF_SSTL15_T_DCI")), Subsignal("dqs_n", Pins("AF18 Y16 AE20 W19 W5 AC1 AB5 AF4"), - IOStandard("DIFF_SSTL15")), - Subsignal("clk_p", Pins("AC9"), IOStandard("DIFF_SSTL15")), - Subsignal("clk_n", Pins("AD9"), IOStandard("DIFF_SSTL15")), + IOStandard("DIFF_SSTL15_T_DCI")), + Subsignal("clk_p", Pins("AC9"), + IOStandard("DIFF_SSTL15"), Misc("IO_BUFFER_TYPE=NONE")), + Subsignal("clk_n", Pins("AD9"), + IOStandard("DIFF_SSTL15"), Misc("IO_BUFFER_TYPE=NONE")), Subsignal("cke", Pins("AB9"), IOStandard("SSTL15")), - #Subsignal("odt", Pins("AA12"), IOStandard("SSTL15")), + Subsignal("odt", Pins("AA12"), IOStandard("SSTL15")), Subsignal("reset_n", Pins("AB20"), IOStandard("LVCMOS15")), Misc("SLEW=FAST"), Misc("VCCAUX_IO=NORMAL")