From cf58550bba7e28c62afbe5d86ea6ceaf8aa6bb25 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 10 Mar 2020 16:05:59 +0100 Subject: [PATCH] targets/Ultrascale+: use USPDDRPHY. --- litex_boards/targets/mercury_xu5.py | 7 +++---- litex_boards/targets/vcu118.py | 9 +++++---- litex_boards/targets/zcu104.py | 7 +++---- 3 files changed, 11 insertions(+), 12 deletions(-) diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py index b447c2d..dc89a5a 100755 --- a/litex_boards/targets/mercury_xu5.py +++ b/litex_boards/targets/mercury_xu5.py @@ -84,12 +84,11 @@ class BaseSoC(SoCSDRAM): # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), + self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), memtype = "DDR4", - sim_device = "ULTRASCALE_PLUS", + sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6, - cmd_latency = 0, - sys_clk_freq = sys_clk_freq) + cmd_latency = 0) self.add_csr("ddrphy") self.add_constant("USDDRPHY", None) sdram_module = MT40A256M16(sys_clk_freq, "1:4") diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py index 2d875bc..ac1ae26 100755 --- a/litex_boards/targets/vcu118.py +++ b/litex_boards/targets/vcu118.py @@ -86,10 +86,11 @@ class BaseSoC(SoCSDRAM): # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram"), - memtype = "DDR4", - sys_clk_freq = sys_clk_freq, - sim_device = "ULTRASCALE_PLUS") + self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram"), + memtype = "DDR4", + sys_clk_freq = sys_clk_freq, + iodelay_clk_freq = 200e6, + cmd_latency = 0) self.add_csr("ddrphy") self.add_constant("USDDRPHY", None) sdram_module = EDY4016A(sys_clk_freq, "1:4") diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py index dd119c0..61275eb 100755 --- a/litex_boards/targets/zcu104.py +++ b/litex_boards/targets/zcu104.py @@ -85,12 +85,11 @@ class BaseSoC(SoCSDRAM): # DDR4 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: - self.submodules.ddrphy = usddrphy.USDDRPHY(platform.request("ddram_32"), # FIXME: use ddram_64 + self.submodules.ddrphy = usddrphy.USPDDRPHY(platform.request("ddram_32"), # FIXME: use ddram_64 memtype = "DDR4", - sim_device = "ULTRASCALE_PLUS", + sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 500e6, - cmd_latency = 1, - sys_clk_freq = sys_clk_freq) + cmd_latency = 1) self.add_csr("ddrphy") self.add_constant("USDDRPHY", None) sdram_module = KVR21SE15S84(sys_clk_freq, "1:4")