diff --git a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py
index 705d784..92fe6e2 100755
--- a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py
+++ b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py
@@ -53,7 +53,7 @@ class _CRG(LiteXModule):
         self.comb += pll.reset.eq(~rst_n | self.rst_pulse)
         pll.register_clkin(clk50, 50e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
-        pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180, name="sdram_clk")
+        pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180)
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
@@ -69,7 +69,7 @@ class BaseSoC(SoCCore):
 
         # SDR SDRAM --------------------------------------------------------------------------------
         if not self.integrated_main_ram_size and sys_clk_freq <= 50e6 :
-            self.specials += ClkOutput("sdram_clk", platform.request("sdram_clock"))
+            self.specials += ClkOutput(ClockSignal(self.cd_sys_ps), platform.request("sdram_clock"))
 
             self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",