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litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py: removed create_clkout name param, updated ClkOutput special

This commit is contained in:
Gwenhael Goavec-Merou 2024-09-10 16:37:12 +02:00
parent 59d32e4283
commit d0c07933bf
1 changed files with 2 additions and 2 deletions
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litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py
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@ -53,7 +53,7 @@ class _CRG(LiteXModule):
self.comb += pll.reset.eq(~rst_n | self.rst_pulse) self.comb += pll.reset.eq(~rst_n | self.rst_pulse)
pll.register_clkin(clk50, 50e6) pll.register_clkin(clk50, 50e6)
pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True)
pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180, name="sdram_clk") pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180)
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
@ -69,7 +69,7 @@ class BaseSoC(SoCCore):
# SDR SDRAM -------------------------------------------------------------------------------- # SDR SDRAM --------------------------------------------------------------------------------
if not self.integrated_main_ram_size and sys_clk_freq <= 50e6 : if not self.integrated_main_ram_size and sys_clk_freq <= 50e6 :
self.specials += ClkOutput("sdram_clk", platform.request("sdram_clock")) self.specials += ClkOutput(ClockSignal(self.cd_sys_ps), platform.request("sdram_clock"))
self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq) self.sdrphy = GENSDRPHY(platform.request("sdram"), sys_clk_freq)
self.add_sdram("sdram", self.add_sdram("sdram",