From d0e1c6fd373233ef09991268c3df4ede684cda0f Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 13 Jun 2024 18:28:12 +0200 Subject: [PATCH] litex_acorn_baseboard_mini: WiP GTPE2_common sharing. --- litex_boards/targets/litex_acorn_baseboard_mini.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/litex_boards/targets/litex_acorn_baseboard_mini.py b/litex_boards/targets/litex_acorn_baseboard_mini.py index 87de2be..aa51a73 100755 --- a/litex_boards/targets/litex_acorn_baseboard_mini.py +++ b/litex_boards/targets/litex_acorn_baseboard_mini.py @@ -136,13 +136,15 @@ class BaseSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- if with_pcie: - assert not with_sata and (not with_ethernet or with_etherbone) + #assert not with_sata and (not with_ethernet or with_etherbone) self.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1_baseboard"), data_width = 64, bar0_size = 0x20000) self.add_pcie(phy=self.pcie_phy, ndmas=1) - platform.toolchain.pre_placement_commands.append("reset_property LOC [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtp_channel.gtpe2_channel_i}}]") - platform.toolchain.pre_placement_commands.append("set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtp_channel.gtpe2_channel_i}}]") + #platform.toolchain.pre_placement_commands.append("reset_property LOC [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtp_channel.gtpe2_channel_i}}]") + #platform.toolchain.pre_placement_commands.append("set_property LOC GTPE2_CHANNEL_X0Y4 [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtp_channel.gtpe2_channel_i}}]") + + platform.toolchain.pre_placement_commands.append("remove_cell [get_cells -hierarchical -filter {{NAME=~pcie_s7/*gtpe2_common_i}}]") # Ethernet / SATA RefClk/Shared-QPLL -------------------------------------------------------