diff --git a/litex_boards/platforms/qmtech_10cl006.py b/litex_boards/platforms/qmtech_10cl006.py new file mode 100644 index 0000000..7f669ed --- /dev/null +++ b/litex_boards/platforms/qmtech_10cl006.py @@ -0,0 +1,162 @@ +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2021 Hans Baier +# SPDX-License-Identifier: BSD-2-Clause + +from litex.build.generic_platform import * +from litex.build.altera import AlteraPlatform +from litex.build.altera.programmer import USBBlaster + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # Clk + ("clk50", 0, Pins("E1"), IOStandard("3.3-V LVTTL")), + + # Button + ("key", 0, Pins("F3"), IOStandard("3.3-V LVTTL")), + ("key", 1, Pins("J6"), IOStandard("3.3-V LVTTL")), + + # Serial + ("serial", 0, + # Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232) + Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10) + Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL")) # GPIO_05 (JP1 Pin 8) + ), + + # SPIFlash (W25Q64) + ("spiflash", 0, + # clk + Subsignal("cs_n", Pins("D2")), + Subsignal("clk", Pins("H1")), + Subsignal("mosi", Pins("C1")), + Subsignal("miso", Pins("H2")), + IOStandard("3.3-V LVTTL"), + ), + + # SDR SDRAM + ("sdram_clock", 0, Pins("Y6"), IOStandard("3.3-V LVTTL")), + ("sdram", 0, + Subsignal("a", Pins( + "R7 T7 R8 T8 R6 T5 R5 T4", + "R4 T3 T6 R3 T2")), + Subsignal("ba", Pins("N8 L8")), + Subsignal("cs_n", Pins("P8")), + Subsignal("cke", Pins("R1")), + Subsignal("ras_n", Pins("M8")), + Subsignal("cas_n", Pins("M7")), + Subsignal("we_n", Pins("P6")), + Subsignal("dq", Pins( + "K5 L3 L4 K6 N3 M6 P3 N5", + "N2 N1 L1 L2 K1 K2 J1 J2")), + Subsignal("dm", Pins("N6 P1")), + IOStandard("3.3-V LVTTL") + ), +] + +# The connectors are named after the daughterboard, not the core board +# because on the different core boards the names vary, but on the +# daughterboard they stay the same, which we need to connect the +# daughterboard peripherals to the core board. +# On this board J2 is U7 and J3 is U8 +_connectors = [ + ("J2", { + # odd row even row + 7: "G1", 8: "G2", + 9: "D1", 10: "C2", + 11: "B1", 12: "F5", + 13: "D3", 14: "C3", + 15: "B3", 16: "A3", + 17: "B4", 18: "A4", + 19: "E5", 20: "A2", + 21: "D4", 22: "E6", + 23: "C6", 24: "D6", + 25: "B5", 26: "A5", + 27: "B6", 28: "A6", + 29: "B7", 30: "A7", + 31: "D8", 32: "C8", + 33: "D9", 34: "C9", + 35: "B8", 36: "A8", + 37: "B9", 38: "A9", + 39: "E9", 40: "E8", + 41: "E11", 42: "E10", + 43: "A10", 44: "B10", + 45: "D12", 46: "D11", + 47: "B11", 48: "A11", + 49: "B12", 50: "A12", + 51: "B13", 52: "A13", + 53: "B14", 54: "A14", + 55: "D14", 56: "C14", + 57: "B16", 58: "A15", + 59: "C16", 60: "C15", + }), + ("J3", { + # odd row even row + 7: "R9", 8: "T9", + 9: "R10", 10: "T10", + 11: "R11", 12: "T11", + 13: "R12", 14: "T12", + 15: "N9", 16: "M9", + 17: "M10", 18: "P9", + 19: "P11", 20: "N11", + 21: "R13", 22: "T13", + 23: "T15", 24: "T14", + 25: "N12", 26: "M11", + 27: "R14", 28: "N13", + 29: "N14", 30: "P14", + 31: "P16", 32: "R16", + 33: "N16", 34: "N15", + 35: "M16", 36: "M15", + 37: "L16", 38: "L15", + 39: "P15", 40: "M12", + 41: "L14", 42: "L13", + 43: "K16", 44: "K15", + 45: "K12", 46: "J12", + 47: "J14", 48: "J13", + 49: "K11", 50: "J11", + 51: "G11", 52: "F11", + 53: "F13", 54: "F14", + 55: "F10", 56: "F9", + 57: "E16", 58: "E15", + 59: "D16", 60: "D15", + }) +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(AlteraPlatform): + default_clk_name = "clk50" + default_clk_period = 1e9/50e6 + core_resources = [ ("user_led", 0, Pins("L9"), IOStandard("3.3-V LVTTL")) ] + + def __init__(self, with_daughterboard=False): + device = "10CL006YU256C8G" + io = _io + connectors = _connectors + + if with_daughterboard: + from litex_boards.platforms.qmtech_daughterboard import QMTechDaughterboard + daughterboard = QMTechDaughterboard(IOStandard("3.3-V LVTTL")) + io += daughterboard.io + connectors += daughterboard.connectors + else: + io += self.core_resources + + AlteraPlatform.__init__(self, device, io, connectors) + + if with_daughterboard: + # an ethernet pin takes K22, so make it available + self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"") + + # Generate PLL clock in STA + self.toolchain.additional_sdc_commands.append("derive_pll_clocks") + # Calculates clock uncertainties + self.toolchain.additional_sdc_commands.append("derive_clock_uncertainty") + + def create_programmer(self): + return USBBlaster() + + def do_finalize(self, fragment): + AlteraPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6) diff --git a/litex_boards/targets/qmtech_10cl006.py b/litex_boards/targets/qmtech_10cl006.py new file mode 100644 index 0000000..294b100 --- /dev/null +++ b/litex_boards/targets/qmtech_10cl006.py @@ -0,0 +1,183 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2021 Hans Baier +# SPDX-License-Identifier: BSD-2-Clause + +import os +import argparse + +from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer + +from litex.build.io import DDROutput + +from litex_boards.platforms import qmtech_10cl006 + +from litex.soc.cores.clock import Cyclone10LPPLL +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser + +from litedram.modules import IS42S16160 +from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY + +from litex.soc.cores.video import VideoVGAPHY +from liteeth.phy.mii import LiteEthPHYMII + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq, with_ethernet, with_vga, sdram_rate="1:1"): + self.rst = Signal() + self.clock_domains.cd_sys = ClockDomain() + + if sdram_rate == "1:2": + self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True) + else: + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) + + if with_ethernet: + self.clock_domains.cd_eth = ClockDomain() + + if with_vga: + self.clock_domains.cd_vga = ClockDomain(reset_less=True) + + # # # + + # Clk / Rst + clk50 = platform.request("clk50") + + # PLL + self.submodules.pll = pll = Cyclone10LPPLL(speedgrade="-C8") + self.comb += pll.reset.eq(self.rst) + pll.register_clkin(clk50, 50e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + if sdram_rate == "1:2": + pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) + # theoretically 90 degrees, but increase to relax timing + pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) + else: + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) + + if with_ethernet: + pll.create_clkout(self.cd_eth, 25e6) + if with_vga: + pll.create_clkout(self.cd_vga, 40e6) + + # SDRAM clock + sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk) + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(50e6), with_daughterboard=False, + with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, + with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, + ident_version=True, sdram_rate="1:1", **kwargs): + platform = qmtech_10cl006.Platform(with_daughterboard=with_daughterboard) + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on QMTECH 10CL006" + (" + Daughterboard" if with_daughterboard else ""), + ident_version = ident_version, + **kwargs) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, + sys_clk_freq, with_ethernet or with_etherbone, + with_video_terminal or with_video_framebuffer, + sdram_rate=sdram_rate) + + # SDR SDRAM -------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: + sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY + self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) + self.add_sdram("sdram", + phy = self.sdrphy, + module = IS42S16160(sys_clk_freq, sdram_rate), + l2_cache_size = kwargs.get("l2_size", 8192) + ) + + # Ethernet / Etherbone --------------------------------------------------------------------- + if with_ethernet or with_etherbone: + self.submodules.ethphy = LiteEthPHYMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) + if with_ethernet: + self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) + if with_etherbone: + self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) + + # Video ------------------------------------------------------------------------------------ + if with_video_terminal or with_video_framebuffer: + self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga") + if with_video_terminal: + self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") + if with_video_framebuffer: + self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga") + + # Leds ------------------------------------------------------------------------------------- + if with_led_chaser: + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + +# Build -------------------------------------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on QMTECH 10CL006") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") + parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate") + parser.add_argument("--with-daughterboard", action="store_true", help="Whether the core board is plugged into the QMTech daughterboard") + ethopts = parser.add_mutually_exclusive_group() + ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") + parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address") + parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting") + sdopts = parser.add_mutually_exclusive_group() + sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") + sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") + parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output") + viopts = parser.add_mutually_exclusive_group() + viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA)") + viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (VGA)") + + builder_args(parser) + soc_core_args(parser) + args = parser.parse_args() + + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_daughterboard = args.with_daughterboard, + with_ethernet = args.with_ethernet, + with_etherbone = args.with_etherbone, + eth_ip = args.eth_ip, + eth_dynamic_ip = args.eth_dynamic_ip, + ident_version = args.no_ident_version, + with_video_terminal = args.with_video_terminal, + with_video_framebuffer = args.with_video_framebuffer, + sdram_rate = args.sdram_rate, + **soc_core_argdict(args) + ) + + if args.with_spi_sdcard: + soc.add_spi_sdcard() + if args.with_sdcard: + soc.add_sdcard() + + builder = Builder(soc, **builder_argdict(args)) + builder.build(run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof")) + +if __name__ == "__main__": + main()