From d28a0c42589dc1db121d461a251ebf0a4453acdb Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 30 Jun 2020 17:37:24 +0200 Subject: [PATCH] targets/pcie: remove DNA/XADC/ICAP that were only on PCIe targets. DNA/XADC/ICAP are demonstrated in LitePCIe repository and should probably be added with a add_xy method. --- litex_boards/targets/acorn_cle_215.py | 17 ----------------- litex_boards/targets/aller.py | 17 ----------------- litex_boards/targets/nereid.py | 17 ----------------- litex_boards/targets/tagus.py | 17 ----------------- 4 files changed, 68 deletions(-) diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py index 3e2ef18..983c70f 100755 --- a/litex_boards/targets/acorn_cle_215.py +++ b/litex_boards/targets/acorn_cle_215.py @@ -35,9 +35,6 @@ from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.clock import * -from litex.soc.cores.dna import DNA -from litex.soc.cores.xadc import XADC -from litex.soc.cores.icap import ICAP from litex.soc.cores.led import LedChaser from litedram.modules import MT41K512M16 @@ -87,20 +84,6 @@ class PCIeSoC(SoCCore): self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") - # DNA -------------------------------------------------------------------------------------- - self.submodules.dna = DNA() - self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) - self.add_csr("dna") - - # XADC ------------------------------------------------------------------------------------- - self.submodules.xadc = XADC() - self.add_csr("xadc") - - # ICAP ------------------------------------------------------------------------------------- - self.submodules.icap = ICAP(platform) - self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) - self.add_csr("icap") - # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py index 157f2b1..a1f276b 100755 --- a/litex_boards/targets/aller.py +++ b/litex_boards/targets/aller.py @@ -18,9 +18,6 @@ from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.clock import * -from litex.soc.cores.dna import DNA -from litex.soc.cores.xadc import XADC -from litex.soc.cores.icap import ICAP from litex.soc.cores.led import LedChaser from litedram.modules import MT41J128M16 @@ -70,20 +67,6 @@ class PCIeSoC(SoCCore): self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") - # DNA -------------------------------------------------------------------------------------- - self.submodules.dna = DNA() - self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) - self.add_csr("dna") - - # XADC ------------------------------------------------------------------------------------- - self.submodules.xadc = XADC() - self.add_csr("xadc") - - # ICAP ------------------------------------------------------------------------------------- - self.submodules.icap = ICAP(platform) - self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) - self.add_csr("icap") - # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"), diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py index b999493..c5d4308 100755 --- a/litex_boards/targets/nereid.py +++ b/litex_boards/targets/nereid.py @@ -18,9 +18,6 @@ from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.clock import * -from litex.soc.cores.dna import DNA -from litex.soc.cores.xadc import XADC -from litex.soc.cores.icap import ICAP from litedram.modules import MT8KTF51264 from litedram.phy import s7ddrphy @@ -67,20 +64,6 @@ class PCIeSoC(SoCCore): self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") - # DNA -------------------------------------------------------------------------------------- - self.submodules.dna = DNA() - self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) - self.add_csr("dna") - - # XADC ------------------------------------------------------------------------------------- - self.submodules.xadc = XADC() - self.add_csr("xadc") - - # ICAP ------------------------------------------------------------------------------------- - self.submodules.icap = ICAP(platform) - self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) - self.add_csr("icap") - # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"), diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py index 4450796..d4068a3 100755 --- a/litex_boards/targets/tagus.py +++ b/litex_boards/targets/tagus.py @@ -18,9 +18,6 @@ from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores.clock import * -from litex.soc.cores.dna import DNA -from litex.soc.cores.xadc import XADC -from litex.soc.cores.icap import ICAP from litex.soc.cores.led import LedChaser from litedram.modules import MT41J128M16 @@ -70,20 +67,6 @@ class PCIeSoC(SoCCore): self.submodules.crg = CRG(platform, sys_clk_freq) self.add_csr("crg") - # DNA -------------------------------------------------------------------------------------- - self.submodules.dna = DNA() - self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) - self.add_csr("dna") - - # XADC ------------------------------------------------------------------------------------- - self.submodules.xadc = XADC() - self.add_csr("xadc") - - # ICAP ------------------------------------------------------------------------------------- - self.submodules.icap = ICAP(platform) - self.icap.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) - self.add_csr("icap") - # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),