From d34c3baf15f7d4731c4be5a46e8aceb888a70e68 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 6 May 2020 16:14:51 +0200 Subject: [PATCH] prog: use different openocd config files for FT232/FT2232. --- litex_boards/platforms/ac701.py | 2 +- litex_boards/platforms/acorn_cle_215.py | 2 +- litex_boards/platforms/aller.py | 2 +- litex_boards/platforms/arty.py | 2 +- litex_boards/platforms/arty_s7.py | 2 +- litex_boards/platforms/genesys2.py | 2 +- litex_boards/platforms/kc705.py | 2 +- litex_boards/platforms/kx2.py | 2 +- litex_boards/platforms/linsn_rv901t.py | 2 +- litex_boards/platforms/mimas_a7.py | 2 +- litex_boards/platforms/nereid.py | 2 +- litex_boards/platforms/nexys4ddr.py | 2 +- litex_boards/platforms/nexys_video.py | 2 +- litex_boards/platforms/sp605.py | 2 +- litex_boards/platforms/tagus.py | 2 +- litex_boards/platforms/vc707.py | 2 +- ...enocd_xilinx_xc6.cfg => openocd_xc6_ft2232.cfg} | 0 litex_boards/prog/openocd_xc6_ft232.cfg | 14 ++++++++++++++ ...enocd_xilinx_xc7.cfg => openocd_xc7_ft2232.cfg} | 0 litex_boards/prog/openocd_xc7_ft232.cfg | 14 ++++++++++++++ 20 files changed, 44 insertions(+), 16 deletions(-) rename litex_boards/prog/{openocd_xilinx_xc6.cfg => openocd_xc6_ft2232.cfg} (100%) create mode 100644 litex_boards/prog/openocd_xc6_ft232.cfg rename litex_boards/prog/{openocd_xilinx_xc7.cfg => openocd_xc7_ft2232.cfg} (100%) create mode 100644 litex_boards/prog/openocd_xc7_ft232.cfg diff --git a/litex_boards/platforms/ac701.py b/litex_boards/platforms/ac701.py index 06dbc15..c0b5b6d 100644 --- a/litex_boards/platforms/ac701.py +++ b/litex_boards/platforms/ac701.py @@ -223,7 +223,7 @@ class Platform(XilinxPlatform): self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]") def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit") + return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a200t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/acorn_cle_215.py b/litex_boards/platforms/acorn_cle_215.py index c2d0e6f..a62c903 100644 --- a/litex_boards/platforms/acorn_cle_215.py +++ b/litex_boards/platforms/acorn_cle_215.py @@ -93,7 +93,7 @@ class Platform(XilinxPlatform): "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit") + return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a200t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/aller.py b/litex_boards/platforms/aller.py index 94abc2b..dc44d4f 100644 --- a/litex_boards/platforms/aller.py +++ b/litex_boards/platforms/aller.py @@ -119,7 +119,7 @@ class Platform(XilinxPlatform): "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit") + return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a200t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/arty.py b/litex_boards/platforms/arty.py index 712cd9a..1f8101d 100644 --- a/litex_boards/platforms/arty.py +++ b/litex_boards/platforms/arty.py @@ -259,7 +259,7 @@ class Platform(XilinxPlatform): def create_programmer(self): bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit" - return OpenOCD("openocd_xilinx_xc7.cfg", bscan_spi) + return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi) def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/arty_s7.py b/litex_boards/platforms/arty_s7.py index 952ffb0..b4ec872 100644 --- a/litex_boards/platforms/arty_s7.py +++ b/litex_boards/platforms/arty_s7.py @@ -212,7 +212,7 @@ class Platform(XilinxPlatform): def create_programmer(self): bscan_spi = "bscan_spi_xc7s50.bit" if "xc7s50" in self.device else "bscan_spi_xc7a25.bit" - return OpenOCD("openocd_xilinx.cfg", bscan_spi) + return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi) def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/genesys2.py b/litex_boards/platforms/genesys2.py index 7e5ebc4..7da31c8 100644 --- a/litex_boards/platforms/genesys2.py +++ b/litex_boards/platforms/genesys2.py @@ -117,7 +117,7 @@ class Platform(XilinxPlatform): XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado") def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit") + return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/kc705.py b/litex_boards/platforms/kc705.py index 394e586..dcb0001 100644 --- a/litex_boards/platforms/kc705.py +++ b/litex_boards/platforms/kc705.py @@ -549,7 +549,7 @@ set_property CONFIG_VOLTAGE 2.5 [current_design] self.toolchain.additional_commands = ["write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a325t.bit") + return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a325t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/kx2.py b/litex_boards/platforms/kx2.py index ae5c385..e1dcc23 100644 --- a/litex_boards/platforms/kx2.py +++ b/litex_boards/platforms/kx2.py @@ -73,7 +73,7 @@ class Platform(XilinxPlatform): XilinxPlatform.__init__(self, " xc7k160tffg676-2", _io, toolchain="vivado") def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7k160t.bit") + return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7k160t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/linsn_rv901t.py b/litex_boards/platforms/linsn_rv901t.py index 78d5fb4..6bec4f1 100644 --- a/litex_boards/platforms/linsn_rv901t.py +++ b/litex_boards/platforms/linsn_rv901t.py @@ -293,7 +293,7 @@ class Platform(XilinxPlatform): XilinxPlatform.__init__(self, "xc6slx16-2-ftg256", _io, _connectors) def create_programmer(self): - return OpenOCD("openocd_xilinx_xc6.cfg", "bscan_spi_xc6slx16.bit") + return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc6slx16.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/mimas_a7.py b/litex_boards/platforms/mimas_a7.py index 207837c..fc1e734 100644 --- a/litex_boards/platforms/mimas_a7.py +++ b/litex_boards/platforms/mimas_a7.py @@ -183,7 +183,7 @@ class Platform(XilinxPlatform): self.add_platform_command("set_property INTERNAL_VREF 0.675 [get_iobanks 34]") def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a50t.bit") + return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a50t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/nereid.py b/litex_boards/platforms/nereid.py index ef618a0..64fd63b 100644 --- a/litex_boards/platforms/nereid.py +++ b/litex_boards/platforms/nereid.py @@ -403,7 +403,7 @@ set_property CONFIG_VOLTAGE 3.3 [current_design] "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7k160t.bit") + return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7k160t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/nexys4ddr.py b/litex_boards/platforms/nexys4ddr.py index e112ca6..060caeb 100644 --- a/litex_boards/platforms/nexys4ddr.py +++ b/litex_boards/platforms/nexys4ddr.py @@ -132,7 +132,7 @@ class Platform(XilinxPlatform): self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a100t.bit") + return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a100t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/nexys_video.py b/litex_boards/platforms/nexys_video.py index c8604e9..6dbb945 100644 --- a/litex_boards/platforms/nexys_video.py +++ b/litex_boards/platforms/nexys_video.py @@ -232,7 +232,7 @@ class Platform(XilinxPlatform): self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 35]") def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit") + return OpenOCD("openocd_xc7_ft2232.cfg", "bscan_spi_xc7a200t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/sp605.py b/litex_boards/platforms/sp605.py index 7fa7cbb..5f9b528 100644 --- a/litex_boards/platforms/sp605.py +++ b/litex_boards/platforms/sp605.py @@ -167,7 +167,7 @@ class Platform(XilinxPlatform): XilinxPlatform.__init__(self, "xc6slx45t-fgg484-3", _io, _connectors, toolchain="ise") def create_programmer(self): - return OpenOCD("openocd_xilinx_xc6.cfg", "bscan_spi_xc6slx45.bit") + return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc6slx45.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/tagus.py b/litex_boards/platforms/tagus.py index a1cef61..c39aee0 100644 --- a/litex_boards/platforms/tagus.py +++ b/litex_boards/platforms/tagus.py @@ -168,7 +168,7 @@ class Platform(XilinxPlatform): "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "bscan_spi_xc7a200t.bit") + return OpenOCD("openocd_xc7_ft232.cfg", "bscan_spi_xc7a200t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/platforms/vc707.py b/litex_boards/platforms/vc707.py index 436e886..b18e752 100644 --- a/litex_boards/platforms/vc707.py +++ b/litex_boards/platforms/vc707.py @@ -644,7 +644,7 @@ class Platform(XilinxPlatform): self.add_platform_command("""set_property CONFIG_VOLTAGE 2.5 [current_design]""") def create_programmer(self): - return OpenOCD("openocd_xilinx_xc7.cfg", "xc7vx485t.bit") + return OpenOCD("openocd_xc7_ft2232.cfg", "xc7vx485t.bit") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) diff --git a/litex_boards/prog/openocd_xilinx_xc6.cfg b/litex_boards/prog/openocd_xc6_ft2232.cfg similarity index 100% rename from litex_boards/prog/openocd_xilinx_xc6.cfg rename to litex_boards/prog/openocd_xc6_ft2232.cfg diff --git a/litex_boards/prog/openocd_xc6_ft232.cfg b/litex_boards/prog/openocd_xc6_ft232.cfg new file mode 100644 index 0000000..54fcc35 --- /dev/null +++ b/litex_boards/prog/openocd_xc6_ft232.cfg @@ -0,0 +1,14 @@ +interface ftdi +ftdi_vid_pid 0x0403 0x6014 +ftdi_channel 0 +ftdi_layout_init 0x00e8 0x60eb +reset_config none + +source [find cpld/xilinx-xc6.cfg] +source [find cpld/jtagspi.cfg] +adapter_khz 25000 + +proc fpga_program {} { + global _CHIPNAME + xc6_program $_CHIPNAME.tap +} diff --git a/litex_boards/prog/openocd_xilinx_xc7.cfg b/litex_boards/prog/openocd_xc7_ft2232.cfg similarity index 100% rename from litex_boards/prog/openocd_xilinx_xc7.cfg rename to litex_boards/prog/openocd_xc7_ft2232.cfg diff --git a/litex_boards/prog/openocd_xc7_ft232.cfg b/litex_boards/prog/openocd_xc7_ft232.cfg new file mode 100644 index 0000000..9034996 --- /dev/null +++ b/litex_boards/prog/openocd_xc7_ft232.cfg @@ -0,0 +1,14 @@ +interface ftdi +ftdi_vid_pid 0x0403 0x6014 +ftdi_channel 0 +ftdi_layout_init 0x00e8 0x60eb +reset_config none + +source [find cpld/xilinx-xc7.cfg] +source [find cpld/jtagspi.cfg] +adapter_khz 25000 + +proc fpga_program {} { + global _CHIPNAME + xc7_program $_CHIPNAME.tap +}