From d39d87b701660947dcbfe308fabe8fc89ff18978 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 7 Sep 2022 12:06:22 +0200 Subject: [PATCH] sipeed_tang_primer_20k: Switch to PHYPadsReducer and enable the 2 modules. --- litex_boards/platforms/sipeed_tang_primer_20k.py | 14 +++++--------- litex_boards/targets/sipeed_tang_primer_20k.py | 7 ++++--- 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/litex_boards/platforms/sipeed_tang_primer_20k.py b/litex_boards/platforms/sipeed_tang_primer_20k.py index 509c5cf..7a3d41b 100644 --- a/litex_boards/platforms/sipeed_tang_primer_20k.py +++ b/litex_boards/platforms/sipeed_tang_primer_20k.py @@ -50,8 +50,7 @@ _io = [ IOStandard("LVCMOS33"), ), - # DDR3 SDRAM IMD128M16R39CG8GNF-125 - # DQ group L cannot work now + # DDR3 SDRAM IMD128M16R39CG8GNF-125. ("ddram", 0, Subsignal("a", Pins("F7 A4 D6 F8 C4 E6 B1 D8 A5 F9 K3 B7 A3 C8"), IOStandard("SSTL15")), @@ -60,17 +59,14 @@ _io = [ Subsignal("cas_n", Pins("R6"), IOStandard("SSTL15")), Subsignal("we_n", Pins("L2"), IOStandard("SSTL15")), Subsignal("cs_n", Pins("P5"), IOStandard("SSTL15")), - Subsignal("dm", Pins("K5"), IOStandard("SSTL15")), - #Subsignal("dm", Pins("G1 K5"), IOStandard("SSTL15")), + Subsignal("dm", Pins("G1 K5"), IOStandard("SSTL15")), Subsignal("dq", Pins( - #"G5 F5 F4 F3 E2 C1 E1 B3", + "G5 F5 F4 F3 E2 C1 E1 B3", "M3 K4 N2 L1 P4 H3 R1 M2"), IOStandard("SSTL15"), Misc("VREF=INTERNAL")), - #Subsignal("dqs_p", Pins("G2 J5"), IOStandard("SSTL15D")), - Subsignal("dqs_p", Pins("J5"), IOStandard("SSTL15D")), - #Subsignal("dqs_n", Pins("G3 K6"), IOStandard("SSTL15D")), - Subsignal("dqs_n", Pins("K6"), IOStandard("SSTL15D")), + Subsignal("dqs_p", Pins("G2 J5"), IOStandard("SSTL15D")), + Subsignal("dqs_n", Pins("G3 K6"), IOStandard("SSTL15D")), Subsignal("clk_p", Pins("J1"), IOStandard("SSTL15D")), Subsignal("clk_n", Pins("J3"), IOStandard("SSTL15D")), Subsignal("cke", Pins("J2"), IOStandard("SSTL15")), diff --git a/litex_boards/targets/sipeed_tang_primer_20k.py b/litex_boards/targets/sipeed_tang_primer_20k.py index a8754b1..662a6cc 100755 --- a/litex_boards/targets/sipeed_tang_primer_20k.py +++ b/litex_boards/targets/sipeed_tang_primer_20k.py @@ -22,7 +22,7 @@ from liteeth.phy.rmii import LiteEthPHYRMII from litex_boards.platforms import sipeed_tang_primer_20k -from liteeth.phy.rmii import LiteEthPHYRMII +from litedram.common import PHYPadsReducer from litedram.modules import MT41J128M16 from litedram.phy import GW2DDRPHY @@ -122,8 +122,9 @@ class BaseSoC(SoCCore): # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = GW2DDRPHY( - platform.request("ddram"), - sys_clk_freq=sys_clk_freq) + pads = PHYPadsReducer(platform.request("ddram"), [0, 1]), + sys_clk_freq = sys_clk_freq + ) self.ddrphy.settings.rtt_nom = "disabled" self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.comb += self.crg.reset.eq(self.ddrphy.init.reset)