From d42af3ea19133c8929a8fd2cb9b42dbaff0fcbc0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 12 Nov 2020 18:07:28 +0100 Subject: [PATCH] targets: add --sys-clk-freq support to all targets. --- litex_boards/targets/ac701.py | 9 ++-- litex_boards/targets/acorn_cle_215.py | 10 +++-- litex_boards/targets/aller.py | 18 +++++--- litex_boards/targets/alveo_u250.py | 15 ++++--- litex_boards/targets/arty.py | 9 +++- litex_boards/targets/arty_s7.py | 10 +++-- litex_boards/targets/c10lprefkit.py | 7 ++- litex_boards/targets/camlink_4k.py | 13 ++++-- litex_boards/targets/colorlight_5a_75x.py | 9 ++-- litex_boards/targets/crosslink_nx_evn.py | 11 +++-- litex_boards/targets/crosslink_nx_vip.py | 10 +++-- litex_boards/targets/de0nano.py | 13 ++++-- litex_boards/targets/de10lite.py | 13 ++++-- litex_boards/targets/de10nano.py | 6 ++- litex_boards/targets/de1soc.py | 10 +++-- litex_boards/targets/de2_115.py | 10 +++-- litex_boards/targets/ecpix5.py | 7 ++- litex_boards/targets/fk33.py | 15 ++++--- litex_boards/targets/fomu.py | 10 +++-- litex_boards/targets/genesys2.py | 9 +++- litex_boards/targets/hadbadge.py | 5 ++- litex_boards/targets/icebreaker.py | 14 +++--- litex_boards/targets/kc705.py | 2 + litex_boards/targets/kcu105.py | 6 ++- litex_boards/targets/kx2.py | 10 +++-- litex_boards/targets/linsn_rv901t.py | 53 ++++++----------------- litex_boards/targets/logicbone.py | 7 +-- litex_boards/targets/mercury_xu5.py | 10 +++-- litex_boards/targets/mimas_a7.py | 7 ++- litex_boards/targets/minispartan6.py | 13 ++++-- litex_boards/targets/mist.py | 13 ++++-- litex_boards/targets/nereid.py | 19 ++++---- litex_boards/targets/netv2.py | 2 + litex_boards/targets/nexys4ddr.py | 8 ++-- litex_boards/targets/nexys_video.py | 8 +++- litex_boards/targets/orangecrab.py | 1 + litex_boards/targets/pano_logic_g2.py | 5 ++- litex_boards/targets/pipistrello.py | 4 +- litex_boards/targets/qmtech_ep4ce15.py | 13 ++++-- litex_boards/targets/tagus.py | 18 +++++--- litex_boards/targets/tec0117.py | 14 +++--- litex_boards/targets/tinyfpga_bx.py | 10 +++-- litex_boards/targets/trellisboard.py | 9 ++-- litex_boards/targets/ulx3s.py | 5 ++- litex_boards/targets/vc707.py | 15 ++++--- litex_boards/targets/vcu118.py | 10 +++-- litex_boards/targets/versa_ecp5.py | 6 ++- litex_boards/targets/xcu1525.py | 2 + litex_boards/targets/zcu104.py | 13 +++--- litex_boards/targets/zybo_z7.py | 10 +++-- 50 files changed, 338 insertions(+), 188 deletions(-) diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py index 7accf14..b144a7a 100755 --- a/litex_boards/targets/ac701.py +++ b/litex_boards/targets/ac701.py @@ -145,17 +145,20 @@ def main(): soc_sdram_args(parser) parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--ethernet-phy", default="rgmii", help="Select Ethernet PHY: rgmii (default) or 1000basex") - parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") - parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") args = parser.parse_args() soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), with_ethernet = args.with_ethernet, ethernet_phy = args.ethernet_phy, with_pcie = args.with_pcie, - **soc_sdram_argdict(args)) + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py index 597e770..082e474 100755 --- a/litex_boards/targets/acorn_cle_215.py +++ b/litex_boards/targets/acorn_cle_215.py @@ -72,9 +72,8 @@ class CRG(Module): # BaseSoC ----------------------------------------------------------------------------------------- class BaseSoC(SoCCore): - def __init__(self, with_pcie=False, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs): platform = acorn_cle_215.Platform() - sys_clk_freq = int(100e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, @@ -124,6 +123,7 @@ def main(): parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--flash", action="store_true", help="Flash bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support (requires SDCard adapter on P2)") @@ -131,7 +131,11 @@ def main(): soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(with_pcie = args.with_pcie, **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_pcie = args.with_pcie, + **soc_sdram_argdict(args) + ) if args.with_spi_sdcard: soc.add_spi_sdcard() diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py index be7630e..e97fb30 100755 --- a/litex_boards/targets/aller.py +++ b/litex_boards/targets/aller.py @@ -56,9 +56,8 @@ class CRG(Module): # BaseSoC ----------------------------------------------------------------------------------------- class BaseSoC(SoCCore): - def __init__(self, with_pcie=False, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs): platform = aller.Platform() - sys_clk_freq = int(100e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, @@ -105,15 +104,20 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Aller") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") - parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_pcie = args.with_pcie, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py index 36ad144..d070eba 100755 --- a/litex_boards/targets/alveo_u250.py +++ b/litex_boards/targets/alveo_u250.py @@ -110,15 +110,20 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Alveo U250") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") - parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_pcie = args.with_pcie, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py index d43c5a9..1e9ea3d 100755 --- a/litex_boards/targets/arty.py +++ b/litex_boards/targets/arty.py @@ -106,6 +106,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") @@ -116,8 +117,12 @@ def main(): args = parser.parse_args() assert not (args.with_ethernet and args.with_etherbone) - soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone, - **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_ethernet = args.with_ethernet, + with_etherbone = args.with_etherbone, + **soc_sdram_argdict(args) + ) assert not (args.with_spi_sdcard and args.with_sdcard) soc.platform.add_extension(arty._sdcard_pmod_io) if args.with_spi_sdcard: diff --git a/litex_boards/targets/arty_s7.py b/litex_boards/targets/arty_s7.py index 9075474..f0c112a 100755 --- a/litex_boards/targets/arty_s7.py +++ b/litex_boards/targets/arty_s7.py @@ -90,14 +90,18 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Arty S7") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") builder_args(parser) soc_sdram_args(parser) vivado_build_args(parser) args = parser.parse_args() - soc = BaseSoC(**soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(**vivado_build_argdict(args), run=args.build) diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py index 843bc6b..c91114e 100755 --- a/litex_boards/targets/c10lprefkit.py +++ b/litex_boards/targets/c10lprefkit.py @@ -109,12 +109,17 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on C10 LP RefKit") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=500e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_ethernet = args.with_ethernet, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index 08d9c7b..6bcee44 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -113,15 +113,20 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Cam Link 4K") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=81e6, help="System clock frequency (default: 81MHz)") + parser.add_argument("--toolchain", default="trellis", help="FPGA toolchain: trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) args = parser.parse_args() - soc = BaseSoC(toolchain=args.toolchain, **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + toolchain = args.toolchain, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} builder.build(**builder_kargs, run=args.build) diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py index df27a1e..0b844c0 100755 --- a/litex_boards/targets/colorlight_5a_75x.py +++ b/litex_boards/targets/colorlight_5a_75x.py @@ -118,7 +118,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, board, revision, with_ethernet=False, with_etherbone=False, eth_phy=0, sys_clk_freq=60e6, use_internal_osc=False, sdram_rate="1:1", **kwargs): + def __init__(self, board, revision, sys_clk_freq=60e6, with_ethernet=False, with_etherbone=False, eth_phy=0, use_internal_osc=False, sdram_rate="1:1", **kwargs): board = board.lower() assert board in ["5a-75b", "5a-75e"] if board == "5a-75b": @@ -179,10 +179,10 @@ def main(): parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--board", default="5a-75b", help="Board type: 5a-75b (default) or 5a-75e") parser.add_argument("--revision", default="7.0", type=str, help="Board revision: 7.0 (default), 6.0 or 6.1") + parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1") - parser.add_argument("--sys-clk-freq", default=60e6, type=float, help="System clock frequency (default: 60MHz)") parser.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator") parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate") builder_args(parser) @@ -192,13 +192,14 @@ def main(): assert not (args.with_ethernet and args.with_etherbone) soc = BaseSoC(board=args.board, revision=args.revision, + sys_clk_freq = int(float(args.sys_clk_freq)), with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, eth_phy = args.eth_phy, - sys_clk_freq = args.sys_clk_freq, use_internal_osc = args.use_internal_osc, sdram_rate = args.sdram_rate, - **soc_core_argdict(args)) + **soc_core_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(**trellis_argdict(args), run=args.build) diff --git a/litex_boards/targets/crosslink_nx_evn.py b/litex_boards/targets/crosslink_nx_evn.py index 34d4398..51ccf63 100755 --- a/litex_boards/targets/crosslink_nx_evn.py +++ b/litex_boards/targets/crosslink_nx_evn.py @@ -66,7 +66,7 @@ class BaseSoC(SoCCore): "sram": 0x40000000, "csr": 0xf0000000, } - def __init__(self, sys_clk_freq, **kwargs): + def __init__(self, sys_clk_freq=int(75e6), **kwargs): platform = crosslink_nx_evn.Platform() platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}") @@ -78,8 +78,8 @@ class BaseSoC(SoCCore): # SoCCore -----------------------------------------_---------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, - ident = "LiteX SoC on Crosslink-NX Evaluation Board", - ident_version = True, + ident = "LiteX SoC on Crosslink-NX Evaluation Board", + ident_version = True, **kwargs) # CRG -------------------------------------------------------------------------------------- @@ -110,7 +110,10 @@ def main(): soc_core_args(parser) args = parser.parse_args() - soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_core_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_core_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder_kargs = {} builder.build(**builder_kargs, run=args.build) diff --git a/litex_boards/targets/crosslink_nx_vip.py b/litex_boards/targets/crosslink_nx_vip.py index a8ad14e..16c46b8 100755 --- a/litex_boards/targets/crosslink_nx_vip.py +++ b/litex_boards/targets/crosslink_nx_vip.py @@ -67,7 +67,7 @@ class BaseSoC(SoCCore): "sram": 0x40000000, "csr": 0xf0000000, } - def __init__(self, sys_clk_freq, hyperram="none", **kwargs): + def __init__(self, sys_clk_freq=int(75e6), hyperram="none", **kwargs): platform = crosslink_nx_vip.Platform() platform.add_platform_command("ldc_set_sysconfig {{MASTER_SPI_PORT=SERIAL}}") @@ -108,14 +108,18 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Crosslink-NX VIP Board") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip: none (default), 0 or 1") parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") + parser.add_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip: none (default), 0 or 1") parser.add_argument("--prog-target", default="direct", help="Programming Target: direct (default) or flash") builder_args(parser) soc_core_args(parser) args = parser.parse_args() - soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), hyperram=args.with_hyperram, **soc_core_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + hyperram = args.with_hyperram, + **soc_core_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder_kargs = {} builder.build(**builder_kargs, run=args.build) diff --git a/litex_boards/targets/de0nano.py b/litex_boards/targets/de0nano.py index be92e25..efe4922 100755 --- a/litex_boards/targets/de0nano.py +++ b/litex_boards/targets/de0nano.py @@ -96,14 +96,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE0-Nano") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") + parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(sdram_rate=args.sdram_rate, **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + sdram_rate = args.sdram_rate, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/de10lite.py b/litex_boards/targets/de10lite.py index 1677345..608e394 100755 --- a/litex_boards/targets/de10lite.py +++ b/litex_boards/targets/de10lite.py @@ -104,14 +104,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Lite") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--with-vga", action="store_true", help="Enable VGA support") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") + parser.add_argument("--with-vga", action="store_true", help="Enable VGA support") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(with_vga=args.with_vga, **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_vga = args.with_vga, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/de10nano.py b/litex_boards/targets/de10nano.py index 781afe3..d606706 100755 --- a/litex_boards/targets/de10nano.py +++ b/litex_boards/targets/de10nano.py @@ -117,17 +117,21 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE10-Nano") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board") parser.add_argument("--with-mister-vga", action="store_true", help="Enable VGA with Mister expansion board") parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate") args = parser.parse_args() builder_args(parser) soc_sdram_args(parser) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), with_mister_sdram = args.with_mister_sdram, with_mister_vga = args.with_mister_vga, sdram_rate = args.sdram_rate, - **soc_sdram_argdict(args)) + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/de1soc.py b/litex_boards/targets/de1soc.py index 574d82c..0583ae9 100755 --- a/litex_boards/targets/de1soc.py +++ b/litex_boards/targets/de1soc.py @@ -79,13 +79,17 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE1-SoC") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(**soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/de2_115.py b/litex_boards/targets/de2_115.py index e108ed0..bc61e9a 100755 --- a/litex_boards/targets/de2_115.py +++ b/litex_boards/targets/de2_115.py @@ -79,13 +79,17 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE2-115") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(**soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/ecpix5.py b/litex_boards/targets/ecpix5.py index 845246e..5d2cd8f 100755 --- a/litex_boards/targets/ecpix5.py +++ b/litex_boards/targets/ecpix5.py @@ -127,6 +127,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ECPIX-5") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") builder_args(parser) @@ -134,7 +135,11 @@ def main(): trellis_args(parser) args = parser.parse_args() - soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_core_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_ethernet = args.with_ethernet, + **soc_core_argdict(args) + ) if args.with_sdcard: soc.add_sdcard() builder = Builder(soc, **builder_argdict(args)) diff --git a/litex_boards/targets/fk33.py b/litex_boards/targets/fk33.py index c002c8d..1d3740d 100755 --- a/litex_boards/targets/fk33.py +++ b/litex_boards/targets/fk33.py @@ -102,15 +102,20 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on FK33") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") - parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") builder_args(parser) soc_core_args(parser) args = parser.parse_args() - soc = BaseSoC(with_pcie=args.with_pcie, **soc_core_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_pcie=args.with_pcie, + **soc_core_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/fomu.py b/litex_boards/targets/fomu.py index 78cc248..49dee26 100755 --- a/litex_boards/targets/fomu.py +++ b/litex_boards/targets/fomu.py @@ -70,9 +70,8 @@ class _CRG(Module): class BaseSoC(SoCCore): mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}} - def __init__(self, bios_flash_offset, **kwargs): + def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), **kwargs): kwargs["uart_name"] = "usb_acm" # Enforce UART to USB-ACM - sys_clk_freq = int(12e6) platform = fomu_pvt.Platform() # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM. @@ -149,13 +148,18 @@ def flash(bios_flash_offset): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Fomu") parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency (default: 12MHz)") parser.add_argument("--bios-flash-offset", default=0x60000, help="BIOS offset in SPI Flash (default: 0x60000)") parser.add_argument("--flash", action="store_true", help="Flash Bitstream") builder_args(parser) soc_core_args(parser) args = parser.parse_args() - soc = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args)) + soc = BaseSoC( + bios_flash_offset = args.bios_flash_offset, + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_core_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py index e03a891..c600d14 100755 --- a/litex_boards/targets/genesys2.py +++ b/litex_boards/targets/genesys2.py @@ -99,6 +99,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") builder_args(parser) @@ -106,8 +107,12 @@ def main(): args = parser.parse_args() assert not (args.with_ethernet and args.with_etherbone) - soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone, - **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_ethernet = args.with_ethernet, + with_etherbone = args.with_etherbone, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/hadbadge.py b/litex_boards/targets/hadbadge.py index a0adf9f..8733f67 100755 --- a/litex_boards/targets/hadbadge.py +++ b/litex_boards/targets/hadbadge.py @@ -94,7 +94,10 @@ def main(): trellis_args(parser) args = parser.parse_args() - soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) + soc = BaseSoC( + toolchain = args.toolchain, + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} builder.build(**builder_kargs, run=args.build) diff --git a/litex_boards/targets/icebreaker.py b/litex_boards/targets/icebreaker.py index 068cd89..f56fa5d 100755 --- a/litex_boards/targets/icebreaker.py +++ b/litex_boards/targets/icebreaker.py @@ -69,9 +69,8 @@ class _CRG(Module): class BaseSoC(SoCCore): mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}} - def __init__(self, bios_flash_offset, **kwargs): - sys_clk_freq = int(24e6) - platform = icebreaker.Platform() + def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), **kwargs): + platform = icebreaker.Platform() platform.add_extension(icebreaker.break_off_pmod) # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM. @@ -125,13 +124,18 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash (default: 0x40000)") parser.add_argument("--flash", action="store_true", help="Flash Bitstream") + parser.add_argument("--sys-clk-freq", default=24e6, help="System clock frequency (default: 24MHz)") + parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash (default: 0x40000)") builder_args(parser) soc_core_args(parser) args = parser.parse_args() - soc = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args)) + soc = BaseSoC( + bios_flash_offset = args.bios_flash_offset, + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_core_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py index 6087fa5..6b612f6 100755 --- a/litex_boards/targets/kc705.py +++ b/litex_boards/targets/kc705.py @@ -145,6 +145,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on KC705") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") @@ -154,6 +155,7 @@ def main(): args = parser.parse_args() soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), with_ethernet = args.with_ethernet, with_pcie = args.with_pcie, with_sata = args.with_sata, diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py index afa36f5..3354365 100755 --- a/litex_boards/targets/kcu105.py +++ b/litex_boards/targets/kcu105.py @@ -122,8 +122,9 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on KCU105") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") @@ -134,6 +135,7 @@ def main(): assert not (args.with_ethernet and args.with_etherbone) soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, with_pcie = args.with_pcie, diff --git a/litex_boards/targets/kx2.py b/litex_boards/targets/kx2.py index e581ad0..0f743aa 100755 --- a/litex_boards/targets/kx2.py +++ b/litex_boards/targets/kx2.py @@ -85,13 +85,17 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on KX2") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 125MHz)") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(**soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py index 42c60e3..d8505b6 100755 --- a/litex_boards/targets/linsn_rv901t.py +++ b/litex_boards/targets/linsn_rv901t.py @@ -51,9 +51,8 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, **kwargs): + def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs): platform = linsn_rv901t.Platform() - sys_clk_freq = int(75e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, @@ -77,61 +76,37 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) + # Ethernet --------------------------------------------------------------------------------- + if with_ethernet: + self.submodules.ethphy = LiteEthPHYRGMII( + clock_pads = self.platform.request("eth_clocks", eth_phy), + pads = self.platform.request("eth", eth_phy)) + self.add_csr("ethphy") + self.add_ethernet(phy=self.ethphy) + # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), sys_clk_freq = sys_clk_freq) self.add_csr("leds") -# EthernetSoC -------------------------------------------------------------------------------------- - -class EthernetSoC(BaseSoC): - mem_map = { - "ethmac": 0xb0000000, - } - mem_map.update(BaseSoC.mem_map) - - def __init__(self, eth_phy=0, **kwargs): - BaseSoC.__init__(self, **kwargs) - - # Ethernet --------------------------------------------------------------------------------- - # phy - self.submodules.ethphy = LiteEthPHYRGMII( - clock_pads = self.platform.request("eth_clocks", eth_phy), - pads = self.platform.request("eth", eth_phy)) - self.add_csr("ethphy") - # mac - self.submodules.ethmac = LiteEthMAC( - phy = self.ethphy, - dw = 32, - interface = "wishbone", - endianness = self.cpu.endianness) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_csr("ethmac") - self.add_interrupt("ethmac") - # timing constraints - self.platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.ethphy.crg.cd_eth_rx.clk, - self.ethphy.crg.cd_eth_tx.clk) - # Build -------------------------------------------------------------------------------------------- def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Linsn RV901T") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY: 0 (default) or 1") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - if args.with_ethernet: - soc = EthernetSoC(eth_phy=args.eth_phy, **soc_sdram_argdict(args)) - else: - soc = BaseSoC(**soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py index ae99d76..d9acd10 100755 --- a/litex_boards/targets/logicbone.py +++ b/litex_boards/targets/logicbone.py @@ -94,8 +94,8 @@ class _CRG(Module): class BaseSoC(SoCCore): def __init__(self, revision="rev0", device="45F", sdram_device="MT41K512M16", - with_ethernet = False, sys_clk_freq = int(75e6), + with_ethernet = False, toolchain = "trellis", **kwargs): platform = logicbone.Platform(revision=revision, device=device ,toolchain=toolchain) @@ -175,10 +175,11 @@ def main(): soc = BaseSoC( toolchain = args.toolchain, device = args.device, + sys_clk_freq = int(float(args.sys_clk_freq)), sdram_device = args.sdram_device, with_ethernet = args.with_ethernet, - sys_clk_freq = int(float(args.sys_clk_freq)), - **soc_sdram_argdict(args)) + **soc_sdram_argdict(args) + ) if args.with_sdcard: soc.add_sdcard() builder = Builder(soc, **builder_argdict(args)) diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py index b300af8..67f35c6 100755 --- a/litex_boards/targets/mercury_xu5.py +++ b/litex_boards/targets/mercury_xu5.py @@ -95,13 +95,17 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Mercury XU5") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(**soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/mimas_a7.py b/litex_boards/targets/mimas_a7.py index 339a447..63c53e1 100755 --- a/litex_boards/targets/mimas_a7.py +++ b/litex_boards/targets/mimas_a7.py @@ -100,13 +100,18 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Mimas A7") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") builder_args(parser) soc_sdram_args(parser) vivado_build_args(parser) args = parser.parse_args() - soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_ethernet = args.with_ethernet, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(**vivado_build_argdict(args), run=args.build) diff --git a/litex_boards/targets/minispartan6.py b/litex_boards/targets/minispartan6.py index 4b5d4cd..6cc1231 100755 --- a/litex_boards/targets/minispartan6.py +++ b/litex_boards/targets/minispartan6.py @@ -99,14 +99,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=80e6, help="System clock frequency (default: 80MHz)") + parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(sdram_rate=args.sdram_rate, **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + sdram_rate = args.sdram_rate, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/mist.py b/litex_boards/targets/mist.py index be01cd0..a600ef1 100755 --- a/litex_boards/targets/mist.py +++ b/litex_boards/targets/mist.py @@ -104,14 +104,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on MIST") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--with-vga", action="store_true", help="Enable VGA support") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") + parser.add_argument("--with-vga", action="store_true", help="Enable VGA support") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(with_vga=args.with_vga, **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_vga=args.with_vga, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py index 931caa9..fb7d840 100755 --- a/litex_boards/targets/nereid.py +++ b/litex_boards/targets/nereid.py @@ -53,9 +53,8 @@ class CRG(Module): # BaseSoC ----------------------------------------------------------------------------------------- class BaseSoC(SoCCore): - def __init__(self, with_pcie=False, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs): platform = nereid.Platform() - sys_clk_freq = int(100e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, @@ -84,7 +83,6 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) - # PCIe ------------------------------------------------------------------------------------- if with_pcie: self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), @@ -97,15 +95,20 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Nereid") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") - parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_pcie = args.with_pcie, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/netv2.py b/litex_boards/targets/netv2.py index 058a580..cf11687 100755 --- a/litex_boards/targets/netv2.py +++ b/litex_boards/targets/netv2.py @@ -118,6 +118,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") @@ -129,6 +130,7 @@ def main(): args = parser.parse_args() soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), with_ethernet = args.with_ethernet, with_pcie = args.with_pcie, **soc_sdram_argdict(args) diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr.py index 8ec21a4..4dd55e8 100755 --- a/litex_boards/targets/nexys4ddr.py +++ b/litex_boards/targets/nexys4ddr.py @@ -108,9 +108,11 @@ def main(): soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), - with_ethernet=args.with_ethernet, - **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_ethernet = args.with_ethernet, + **soc_sdram_argdict(args) + ) assert not (args.with_spi_sdcard and args.with_sdcard) if args.with_spi_sdcard: soc.add_spi_sdcard() diff --git a/litex_boards/targets/nexys_video.py b/litex_boards/targets/nexys_video.py index e769d62..6beea14 100755 --- a/litex_boards/targets/nexys_video.py +++ b/litex_boards/targets/nexys_video.py @@ -130,6 +130,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Nexys Video") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") @@ -138,7 +139,12 @@ def main(): soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(with_ethernet=args.with_ethernet, with_sata=args.with_sata, **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_ethernet = args.with_ethernet, + with_sata = args.with_sata, + **soc_sdram_argdict(args) + ) assert not (args.with_spi_sdcard and args.with_sdcard) if args.with_spi_sdcard: soc.add_spi_sdcard() diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index 3e684a0..24f9b46 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -71,6 +71,7 @@ class _CRG(Module): self.comb += reset_timer.wait.eq(~rst_n) self.comb += platform.request("rst_n").eq(reset_timer.done) + class _CRGSDRAM(Module): def __init__(self, platform, sys_clk_freq, with_usb_pll=False): self.clock_domains.cd_init = ClockDomain() diff --git a/litex_boards/targets/pano_logic_g2.py b/litex_boards/targets/pano_logic_g2.py index ebda64f..57c1d2e 100755 --- a/litex_boards/targets/pano_logic_g2.py +++ b/litex_boards/targets/pano_logic_g2.py @@ -83,6 +83,7 @@ def main(): parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--revision", default="c", help="Board revision c (default) or b") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") builder_args(parser) @@ -92,9 +93,11 @@ def main(): assert not (args.with_ethernet and args.with_etherbone) soc = BaseSoC( revision = args.revision, + sys_clk_freq = int(float(args.sys_clk_freq)), with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, - **soc_core_argdict(args)) + **soc_core_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/pipistrello.py b/litex_boards/targets/pipistrello.py index 4cae76c..4fd01aa 100755 --- a/litex_boards/targets/pipistrello.py +++ b/litex_boards/targets/pipistrello.py @@ -200,8 +200,8 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Pipistrello") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() diff --git a/litex_boards/targets/qmtech_ep4ce15.py b/litex_boards/targets/qmtech_ep4ce15.py index 57e498b..7245081 100755 --- a/litex_boards/targets/qmtech_ep4ce15.py +++ b/litex_boards/targets/qmtech_ep4ce15.py @@ -96,14 +96,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on QMTECH EP4CE15") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") + parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(sdram_rate=args.sdram_rate, **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + sdram_rate = args.sdram_rate, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py index 9e584a5..f6999f4 100755 --- a/litex_boards/targets/tagus.py +++ b/litex_boards/targets/tagus.py @@ -57,9 +57,8 @@ class CRG(Module): # BaseSoC ----------------------------------------------------------------------------------------- class BaseSoC(SoCCore): - def __init__(self, with_pcie=False, **kwargs): + def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, **kwargs): platform = tagus.Platform() - sys_clk_freq = int(100e6) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, @@ -106,15 +105,20 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Tagus") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") - parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_pcie = args.with_pcie, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/tec0117.py b/litex_boards/targets/tec0117.py index 56d9b42..ab0e763 100755 --- a/litex_boards/targets/tec0117.py +++ b/litex_boards/targets/tec0117.py @@ -27,9 +27,8 @@ mB = 1024*kB class BaseSoC(SoCCore): mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}} - def __init__(self, bios_flash_offset, **kwargs): - platform = tec0117.Platform() - sys_clk_freq = int(1e9/platform.default_clk_period) + def __init__(self, bios_flash_offset, sys_clk_freq=int(12e6), **kwargs): + platform = tec0117.Platform() # SoC can have littel a bram, as a treat kwargs["integrated_sram_size"] = 2048*2 @@ -97,8 +96,6 @@ def flash(offset, path): print("Programming flash...") dev.write(offset, bios) - - # Build -------------------------------------------------------------------------------------------- def main(): @@ -107,11 +104,16 @@ def main(): parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--bios-flash-offset", default=0x00000, help="BIOS offset in SPI Flash (0x00000 default)") parser.add_argument("--flash", action="store_true", help="Flash BIOS") + parser.add_argument("--sys-clk-freq", default=12e6, help="System clock frequency (default: 12MHz)") builder_args(parser) soc_core_args(parser) args = parser.parse_args() - soc = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args)) + soc= BaseSoC( + bios_flash_offset = args.bios_flash_offset, + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_core_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/tinyfpga_bx.py b/litex_boards/targets/tinyfpga_bx.py index 32a99f1..52fb789 100755 --- a/litex_boards/targets/tinyfpga_bx.py +++ b/litex_boards/targets/tinyfpga_bx.py @@ -29,8 +29,7 @@ mB = 1024*kB class BaseSoC(SoCCore): mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}} - def __init__(self, bios_flash_offset, **kwargs): - sys_clk_freq = int(16e6) + def __init__(self, bios_flash_offset, sys_clk_freq=int(16e6), **kwargs): platform = tinyfpga_bx.Platform() # Disable Integrated ROM since too large for iCE40. @@ -70,11 +69,16 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on TinyFPGA BX") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--bios-flash-offset", default=0x60000, help="BIOS offset in SPI Flash (default: 0x60000)") + parser.add_argument("--sys-clk-freq", default=16e6, help="System clock frequency (default: 16MHz)") builder_args(parser) soc_core_args(parser) args = parser.parse_args() - soc = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args)) + soc = BaseSoC( + bios_flash_offset = args.bios_flash_offset, + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_core_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index 3d14055..9840411 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -54,6 +54,7 @@ class _CRG(Module): pll.register_clkin(clk12, 12e6) pll.create_clkout(self.cd_sys, sys_clk_freq) + class _CRGSDRAM(Module): def __init__(self, platform, sys_clk_freq): self.rst = Signal() @@ -172,9 +173,11 @@ def main(): trellis_args(parser) args = parser.parse_args() - soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), - with_ethernet=args.with_ethernet, - **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_ethernet = args.with_ethernet, + **soc_sdram_argdict(args) + ) assert not (args.with_spi_sdcard and args.with_sdcard) if args.with_spi_sdcard: soc.add_spi_sdcard() diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py index b68e7a6..74d8107 100755 --- a/litex_boards/targets/ulx3s.py +++ b/litex_boards/targets/ulx3s.py @@ -144,7 +144,10 @@ def main(): trellis_args(parser) args = parser.parse_args() - soc = BaseSoC(device=args.device, revision=args.revision, toolchain=args.toolchain, + soc = BaseSoC( + device = args.device, + revision = args.revision, + toolchain = args.toolchain, sys_clk_freq = int(float(args.sys_clk_freq)), sdram_module_cls = args.sdram_module, sdram_rate = args.sdram_rate, diff --git a/litex_boards/targets/vc707.py b/litex_boards/targets/vc707.py index 51befd1..3c23dc0 100755 --- a/litex_boards/targets/vc707.py +++ b/litex_boards/targets/vc707.py @@ -95,15 +95,20 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on VC707") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") - parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(with_pcie_=args.with_pcie, **soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_pcie_ = args.with_pcie, + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py index d63dabc..efff26d 100755 --- a/litex_boards/targets/vcu118.py +++ b/litex_boards/targets/vcu118.py @@ -95,13 +95,17 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on VCU118") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(**soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index cd37590..85f287f 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -148,13 +148,15 @@ def main(): args = parser.parse_args() assert not (args.with_ethernet and args.with_etherbone) - soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), device = args.device, with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, eth_phy = args.eth_phy, toolchain = args.toolchain, - **soc_sdram_argdict(args)) + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} builder.build(**builder_kargs, run=args.build) diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py index 7a284ff..4902021 100755 --- a/litex_boards/targets/xcu1525.py +++ b/litex_boards/targets/xcu1525.py @@ -110,6 +110,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on XCU1525") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") parser.add_argument("--ddram-channel", default="0", help="DDRAM channel (default: 0)") parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") @@ -118,6 +119,7 @@ def main(): args = parser.parse_args() soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), ddram_channel = int(args.ddram_channel, 0), with_pcie = args.with_pcie, **soc_sdram_argdict(args)) diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py index aa7a5e3..e12caa4 100755 --- a/litex_boards/targets/zcu104.py +++ b/litex_boards/targets/zcu104.py @@ -86,9 +86,6 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) - self.submodules.i2c = I2CMaster(platform.request("i2c")) - self.add_csr("i2c") - # Leds ------------------------------------------------------------------------------------- self.submodules.leds = LedChaser( pads = platform.request_all("user_led"), @@ -99,13 +96,17 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ZCU104") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() - soc = BaseSoC(**soc_sdram_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_sdram_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) diff --git a/litex_boards/targets/zybo_z7.py b/litex_boards/targets/zybo_z7.py index e845263..db59bfb 100755 --- a/litex_boards/targets/zybo_z7.py +++ b/litex_boards/targets/zybo_z7.py @@ -84,14 +84,18 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Zybo Z7") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") builder_args(parser) soc_core_args(parser) vivado_build_args(parser) args = parser.parse_args() - soc = BaseSoC(**soc_core_argdict(args)) + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + **soc_core_argdict(args) + ) builder = Builder(soc, **builder_argdict(args)) builder.build(**vivado_build_argdict(args), run=args.build)