From d4b2461b5aa6089b7afe92390b01433b9ea81ff5 Mon Sep 17 00:00:00 2001 From: Shawn Anastasio Date: Fri, 21 Oct 2022 14:15:27 -0500 Subject: [PATCH] platforms/nexys4*: Update part name Symbiflow/f4pga don't recognize the part name xc7a100t-CSG324-1, so change it to xc7a100tcsg324-1 which works with both f4pga and Vivado. --- litex_boards/platforms/digilent_nexys4.py | 2 +- litex_boards/platforms/digilent_nexys4ddr.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/platforms/digilent_nexys4.py b/litex_boards/platforms/digilent_nexys4.py index ae8e525..382b577 100644 --- a/litex_boards/platforms/digilent_nexys4.py +++ b/litex_boards/platforms/digilent_nexys4.py @@ -220,7 +220,7 @@ class Platform(XilinxPlatform): default_clk_period = 1e9/100e6 def __init__(self, toolchain="vivado"): - XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, _connectors, toolchain=toolchain) + XilinxPlatform.__init__(self, "xc7a100tcsg324-1", _io, _connectors, toolchain=toolchain) self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") def create_programmer(self): diff --git a/litex_boards/platforms/digilent_nexys4ddr.py b/litex_boards/platforms/digilent_nexys4ddr.py index 0f7ad4b..f904a52 100644 --- a/litex_boards/platforms/digilent_nexys4ddr.py +++ b/litex_boards/platforms/digilent_nexys4ddr.py @@ -183,7 +183,7 @@ class Platform(XilinxPlatform): default_clk_period = 1e9/100e6 def __init__(self, toolchain="vivado"): - XilinxPlatform.__init__(self, "xc7a100t-CSG324-1", _io, _connectors, toolchain=toolchain) + XilinxPlatform.__init__(self, "xc7a100tcsg324-1", _io, _connectors, toolchain=toolchain) self.add_platform_command("set_property INTERNAL_VREF 0.900 [get_iobanks 34]") def create_programmer(self):