diff --git a/litex_boards/platforms/taobao_a_e115fb.py b/litex_boards/platforms/sitlinv_a_e115fb.py similarity index 100% rename from litex_boards/platforms/taobao_a_e115fb.py rename to litex_boards/platforms/sitlinv_a_e115fb.py diff --git a/litex_boards/platforms/aliexpress_stlv7325.py b/litex_boards/platforms/sitlinv_stlv7325.py similarity index 100% rename from litex_boards/platforms/aliexpress_stlv7325.py rename to litex_boards/platforms/sitlinv_stlv7325.py diff --git a/litex_boards/targets/taobao_a_e115fb.py b/litex_boards/targets/sitlinv_a_e115fb.py similarity index 96% rename from litex_boards/targets/taobao_a_e115fb.py rename to litex_boards/targets/sitlinv_a_e115fb.py index b2eb2f1..caa25f1 100755 --- a/litex_boards/targets/taobao_a_e115fb.py +++ b/litex_boards/targets/sitlinv_a_e115fb.py @@ -11,7 +11,7 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex.gen import LiteXModule -from litex_boards.platforms import taobao_a_e115fb +from litex_boards.platforms import sitlinv_a_e115fb from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * @@ -41,7 +41,7 @@ class _CRG(LiteXModule): class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, **kwargs): - platform = taobao_a_e115fb.Platform() + platform = sitlinv_a_e115fb.Platform() # CRG -------------------------------------------------------------------------------------- self.crg = _CRG(platform, sys_clk_freq) diff --git a/litex_boards/targets/aliexpress_stlv7325.py b/litex_boards/targets/sitlinv_stlv7325.py similarity index 98% rename from litex_boards/targets/aliexpress_stlv7325.py rename to litex_boards/targets/sitlinv_stlv7325.py index ab0b7ef..8b1dbcf 100755 --- a/litex_boards/targets/aliexpress_stlv7325.py +++ b/litex_boards/targets/sitlinv_stlv7325.py @@ -15,7 +15,7 @@ from migen import * from litex.gen import LiteXModule -from litex_boards.platforms import aliexpress_stlv7325 +from litex_boards.platforms import sitlinv_stlv7325 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -66,7 +66,7 @@ class BaseSoC(SoCCore): with_pcie = False, with_sata = False, **kwargs): - platform = aliexpress_stlv7325.Platform() + platform = sitlinv_stlv7325.Platform() # CRG -------------------------------------------------------------------------------------- self.crg = _CRG(platform, sys_clk_freq)