diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py
index 78c8a81..4ac3d2e 100755
--- a/litex_boards/targets/ac701.py
+++ b/litex_boards/targets/ac701.py
@@ -50,7 +50,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_idelay,    200e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/acorn_cle_215.py b/litex_boards/targets/acorn_cle_215.py
index a7dc5fd..a02b2c5 100755
--- a/litex_boards/targets/acorn_cle_215.py
+++ b/litex_boards/targets/acorn_cle_215.py
@@ -66,7 +66,7 @@ class CRG(Module):
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_idelay,    200e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py
index fa96adc..1dd5e36 100755
--- a/litex_boards/targets/aller.py
+++ b/litex_boards/targets/aller.py
@@ -50,7 +50,7 @@ class CRG(Module):
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_idelay,    200e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/alveo_u250.py b/litex_boards/targets/alveo_u250.py
index ad50674..8bb72c9 100755
--- a/litex_boards/targets/alveo_u250.py
+++ b/litex_boards/targets/alveo_u250.py
@@ -44,7 +44,7 @@ class _CRG(Module):
         pll.register_clkin(platform.request("clk300", 0), 300e6)
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
         pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.specials += [
             Instance("BUFGCE_DIV", name="main_bufgce_div",
diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py
index 94c8718..3d153fa 100755
--- a/litex_boards/targets/arty.py
+++ b/litex_boards/targets/arty.py
@@ -47,7 +47,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_idelay,    200e6)
         pll.create_clkout(self.cd_eth,       25e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/arty_s7.py b/litex_boards/targets/arty_s7.py
index 46f460b..65f56e7 100755
--- a/litex_boards/targets/arty_s7.py
+++ b/litex_boards/targets/arty_s7.py
@@ -45,7 +45,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_idelay,    200e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/fk33.py b/litex_boards/targets/fk33.py
index 6ce4c69..80b84a9 100755
--- a/litex_boards/targets/fk33.py
+++ b/litex_boards/targets/fk33.py
@@ -38,7 +38,7 @@ class _CRG(Module):
         self.comb += pll.reset.eq(self.rst)
         pll.register_clkin(platform.request("clk200"), 200e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py
index 9d9d51c..79bd6ee 100755
--- a/litex_boards/targets/genesys2.py
+++ b/litex_boards/targets/genesys2.py
@@ -41,7 +41,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
         pll.create_clkout(self.cd_idelay, 200e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py
index 1c30876..c4031b0 100755
--- a/litex_boards/targets/kc705.py
+++ b/litex_boards/targets/kc705.py
@@ -46,7 +46,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
         pll.create_clkout(self.cd_idelay, 200e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py
index f84707d..58aba66 100755
--- a/litex_boards/targets/kcu105.py
+++ b/litex_boards/targets/kcu105.py
@@ -47,7 +47,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
         pll.create_clkout(self.cd_idelay, 200e6, with_reset=False)
         pll.create_clkout(self.cd_eth,    200e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.specials += [
             Instance("BUFGCE_DIV", name="main_bufgce_div",
diff --git a/litex_boards/targets/kx2.py b/litex_boards/targets/kx2.py
index 504b913..8b6b143 100755
--- a/litex_boards/targets/kx2.py
+++ b/litex_boards/targets/kx2.py
@@ -39,7 +39,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
         pll.create_clkout(self.cd_idelay, 200e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/litefury.py b/litex_boards/targets/litefury.py
index 07a0b0d..794418f 100755
--- a/litex_boards/targets/litefury.py
+++ b/litex_boards/targets/litefury.py
@@ -50,7 +50,7 @@ class CRG(Module):
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_idelay,    200e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py
index f1164a6..378ab60 100755
--- a/litex_boards/targets/mercury_xu5.py
+++ b/litex_boards/targets/mercury_xu5.py
@@ -40,7 +40,7 @@ class _CRG(Module):
         pll.register_clkin(platform.request("clk100"), 100e6)
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
         pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.specials += [
             Instance("BUFGCE_DIV", name="main_bufgce_div",
diff --git a/litex_boards/targets/mimas_a7.py b/litex_boards/targets/mimas_a7.py
index 2181fbb..31ad0fe 100755
--- a/litex_boards/targets/mimas_a7.py
+++ b/litex_boards/targets/mimas_a7.py
@@ -45,7 +45,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_idelay,    200e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/minispartan6.py b/litex_boards/targets/minispartan6.py
index 4c0df18..b82d69a 100755
--- a/litex_boards/targets/minispartan6.py
+++ b/litex_boards/targets/minispartan6.py
@@ -55,7 +55,7 @@ class _CRG(Module):
             pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=90)
         else:
             pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         # SDRAM clock
         sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py
index 7a37ef4..0972517 100755
--- a/litex_boards/targets/nereid.py
+++ b/litex_boards/targets/nereid.py
@@ -47,7 +47,7 @@ class CRG(Module):
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
         pll.create_clkout(self.cd_idelay, 200e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/netv2.py b/litex_boards/targets/netv2.py
index 10e0992..327a321 100755
--- a/litex_boards/targets/netv2.py
+++ b/litex_boards/targets/netv2.py
@@ -55,7 +55,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_idelay,    200e6)
         pll.create_clkout(self.cd_clk100,    100e6)
         pll.create_clkout(self.cd_eth,       50e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr.py
index 35e336a..e925365 100755
--- a/litex_boards/targets/nexys4ddr.py
+++ b/litex_boards/targets/nexys4ddr.py
@@ -49,7 +49,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_idelay,    200e6)
         pll.create_clkout(self.cd_eth,       50e6)
         pll.create_clkout(self.cd_vga,       25e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/nexys_video.py b/litex_boards/targets/nexys_video.py
index 9cfa8d7..ccf21aa 100755
--- a/litex_boards/targets/nexys_video.py
+++ b/litex_boards/targets/nexys_video.py
@@ -45,7 +45,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_idelay,    200e6)
         pll.create_clkout(self.cd_clk100,    100e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/pano_logic_g2.py b/litex_boards/targets/pano_logic_g2.py
index e9374ce..406c3d3 100755
--- a/litex_boards/targets/pano_logic_g2.py
+++ b/litex_boards/targets/pano_logic_g2.py
@@ -39,7 +39,7 @@ class _CRG(Module):
         self.comb += pll.reset.eq(~platform.request("user_btn_n") | self.rst)
         pll.register_clkin(platform.request("clk125"), 125e6)
         pll.create_clkout(self.cd_sys, clk_freq)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
diff --git a/litex_boards/targets/redpitaya.py b/litex_boards/targets/redpitaya.py
index 15f3ab0..b594447 100755
--- a/litex_boards/targets/redpitaya.py
+++ b/litex_boards/targets/redpitaya.py
@@ -41,7 +41,7 @@ class _CRG(Module):
             self.comb += pll.reset.eq(self.rst)
             pll.register_clkin(platform.request(platform.default_clk_name), platform.default_clk_freq)
             pll.create_clkout(self.cd_sys,      sys_clk_freq)
-            platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+            platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
diff --git a/litex_boards/targets/sds1104xe.py b/litex_boards/targets/sds1104xe.py
index 46efde4..cd0a462 100755
--- a/litex_boards/targets/sds1104xe.py
+++ b/litex_boards/targets/sds1104xe.py
@@ -54,7 +54,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_idelay,    200e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py
index 3b1118f..e819f2b 100755
--- a/litex_boards/targets/tagus.py
+++ b/litex_boards/targets/tagus.py
@@ -51,7 +51,7 @@ class CRG(Module):
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
         pll.create_clkout(self.cd_idelay,    200e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/vc707.py b/litex_boards/targets/vc707.py
index a59beab..a08b443 100755
--- a/litex_boards/targets/vc707.py
+++ b/litex_boards/targets/vc707.py
@@ -42,7 +42,7 @@ class _CRG(Module):
         pll.create_clkout(self.cd_sys,    sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,  4*sys_clk_freq)
         pll.create_clkout(self.cd_idelay, 200e6)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay)
 
diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py
index 3585128..ea90331 100755
--- a/litex_boards/targets/vcu118.py
+++ b/litex_boards/targets/vcu118.py
@@ -41,7 +41,7 @@ class _CRG(Module):
         pll.register_clkin(platform.request("clk125"), 125e6)
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
         pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.specials += [
             Instance("BUFGCE_DIV", name="main_bufgce_div",
diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py
index 85e6bb2..804c5a7 100755
--- a/litex_boards/targets/xcu1525.py
+++ b/litex_boards/targets/xcu1525.py
@@ -43,7 +43,7 @@ class _CRG(Module):
         pll.register_clkin(platform.request("clk300", ddram_channel), 300e6)
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
         pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.specials += [
             Instance("BUFGCE_DIV", name="main_bufgce_div",
diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py
index 63a9ad9..55ba03d 100755
--- a/litex_boards/targets/zcu104.py
+++ b/litex_boards/targets/zcu104.py
@@ -42,7 +42,7 @@ class _CRG(Module):
         pll.register_clkin(platform.request("clk125"), 125e6)
         pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
         pll.create_clkout(self.cd_idelay, 500e6, with_reset=False)
-        platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+        platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
         self.specials += [
             Instance("BUFGCE_DIV", name="main_bufgce_div",
diff --git a/litex_boards/targets/zybo_z7.py b/litex_boards/targets/zybo_z7.py
index 971ef69..a377c0c 100755
--- a/litex_boards/targets/zybo_z7.py
+++ b/litex_boards/targets/zybo_z7.py
@@ -40,7 +40,7 @@ class _CRG(Module):
             self.comb += pll.reset.eq(self.rst)
             pll.register_clkin(platform.request("clk125"), 125e6)
             pll.create_clkout(self.cd_sys, sys_clk_freq)
-            platform.add_false_path_constraints(pll.clkin, self.cd_sys.clk)
+            platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.
 
 # BaseSoC ------------------------------------------------------------------------------------------