From d8b006568a836fbfd6daf768c1e89051c68478a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Chandler=20Kl=C3=BCser?= Date: Fri, 1 Sep 2023 04:53:07 -0300 Subject: [PATCH] Update qmtech_artix7_fgg676.py --- litex_boards/platforms/qmtech_artix7_fgg676.py | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/litex_boards/platforms/qmtech_artix7_fgg676.py b/litex_boards/platforms/qmtech_artix7_fgg676.py index 73156e3..45d3f1e 100644 --- a/litex_boards/platforms/qmtech_artix7_fgg676.py +++ b/litex_boards/platforms/qmtech_artix7_fgg676.py @@ -160,6 +160,12 @@ class Platform(Xilinx7SeriesPlatform): io += daughterboard.io connectors += daughterboard.connectors + if with_rp2040_daughterboard: + from litex_boards.platforms.qmtech_rp2040_daughterboard import QMTechDaughterboard + daughterboard = QMTechDaughterboard(IOStandard("LVCMOS33")) + io += daughterboard.io + connectors += daughterboard.connectors + Xilinx7SeriesPlatform.__init__(self, device, io, connectors, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", @@ -179,4 +185,4 @@ class Platform(Xilinx7SeriesPlatform): def do_finalize(self, fragment): Xilinx7SeriesPlatform.do_finalize(self, fragment) - self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6) \ No newline at end of file + self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6)