From d8de4fbdfbdee403e15c1eafa1c74209edcef190 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 27 Feb 2020 11:06:53 +0100
Subject: [PATCH] platforms/targets: keep in sync with LiteX

---
 litex_boards/platforms/netv2.py | 36 +++++++++++++++++++++++++++++++--
 litex_boards/targets/arty.py    |  7 +++++--
 2 files changed, 39 insertions(+), 4 deletions(-)

diff --git a/litex_boards/platforms/netv2.py b/litex_boards/platforms/netv2.py
index 786dee3..2670fd0 100644
--- a/litex_boards/platforms/netv2.py
+++ b/litex_boards/platforms/netv2.py
@@ -71,6 +71,37 @@ _io = [
         Misc("SLEW=FAST"),
     ),
 
+    # pcie
+    ("pcie_x1", 0,
+        Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")),
+        Subsignal("clk_p", Pins("F10")),
+        Subsignal("clk_n", Pins("E10")),
+        Subsignal("rx_p", Pins("D11")),
+        Subsignal("rx_n", Pins("C11")),
+        Subsignal("tx_p", Pins("D5")),
+        Subsignal("tx_n", Pins("C5"))
+    ),
+
+    ("pcie_x2", 0,
+        Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")),
+        Subsignal("clk_p", Pins("F10")),
+        Subsignal("clk_n", Pins("E10")),
+        Subsignal("rx_p", Pins("D11 B10")),
+        Subsignal("rx_n", Pins("C11 A10")),
+        Subsignal("tx_p", Pins("D5 B6")),
+        Subsignal("tx_n", Pins("C5 A6"))
+    ),
+
+    ("pcie_x4", 0,
+        Subsignal("rst_n", Pins("E18"), IOStandard("LVCMOS33")),
+        Subsignal("clk_p", Pins("F10")),
+        Subsignal("clk_n", Pins("E10")),
+        Subsignal("rx_p", Pins("D11 B10 D9 B8")),
+        Subsignal("rx_n", Pins("C11 A10 C9 A8")),
+        Subsignal("tx_p", Pins("D5 B6 D7 B4")),
+        Subsignal("tx_n", Pins("C5 A6 C7 A4"))
+    ),
+
     # ethernet
     ("eth_clocks", 0,
         Subsignal("ref_clk", Pins("D17")),
@@ -156,5 +187,6 @@ class Platform(XilinxPlatform):
     default_clk_name = "clk50"
     default_clk_period = 1e9/50e6
 
-    def __init__(self):
-        XilinxPlatform.__init__(self, "xc7a35t-fgg484-2", _io, toolchain="vivado")
+    def __init__(self, device="xc7a35t"):
+        assert device in ["xc7a35t", "xc7a100t"]
+        XilinxPlatform.__init__(self, device + "-fgg484-2", _io, toolchain="vivado")
diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py
index a822f93..aa8a161 100755
--- a/litex_boards/targets/arty.py
+++ b/litex_boards/targets/arty.py
@@ -148,8 +148,11 @@ def main():
     args = parser.parse_args()
 
     assert not (args.with_ethernet and args.with_etherbone)
-    cls = EthernetSoC if args.with_ethernet else BaseSoC
-    cls = EtherboneSoC if args.with_etherbone else BaseSoC
+    cls = BaseSoC
+    if args.with_ethernet:
+        cls = EthernetSoC
+    if args.with_etherbone:
+        cls = EtherboneSoC
     soc = cls(**soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build(**vivado_build_argdict(args))