diff --git a/litex_boards/targets/radiona_ulx3s.py b/litex_boards/targets/radiona_ulx3s.py
index c3e0622..2205430 100755
--- a/litex_boards/targets/radiona_ulx3s.py
+++ b/litex_boards/targets/radiona_ulx3s.py
@@ -112,11 +112,10 @@ class BaseSoC(SoCCore):
             sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
-                phy              = self.sdrphy,
-                module           = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate),
-                size             = 0x40000000,
-                l2_cache_size    = kwargs.get("l2_size", 8192),
-                l2_cache_reverse = False
+                phy           = self.sdrphy,
+                module        = getattr(litedram_modules, sdram_module_cls)(sys_clk_freq, sdram_rate),
+                size          = 0x40000000,
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Video ------------------------------------------------------------------------------------
diff --git a/litex_boards/targets/scarabhardware_minispartan6.py b/litex_boards/targets/scarabhardware_minispartan6.py
index 36f2184..fe57f60 100755
--- a/litex_boards/targets/scarabhardware_minispartan6.py
+++ b/litex_boards/targets/scarabhardware_minispartan6.py
@@ -86,10 +86,9 @@ class BaseSoC(SoCCore):
             sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
             self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq)
             self.add_sdram("sdram",
-                phy              = self.sdrphy,
-                module           = AS4C16M16(sys_clk_freq, sdram_rate),
-                l2_cache_size    = kwargs.get("l2_size", 8192),
-                l2_cache_reverse = False
+                phy           = self.sdrphy,
+                module        = AS4C16M16(sys_clk_freq, sdram_rate),
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Video ------------------------------------------------------------------------------------
diff --git a/litex_boards/targets/siglent_sds1104xe.py b/litex_boards/targets/siglent_sds1104xe.py
index 7e8bc3f..326a18b 100755
--- a/litex_boards/targets/siglent_sds1104xe.py
+++ b/litex_boards/targets/siglent_sds1104xe.py
@@ -88,10 +88,9 @@ class BaseSoC(SoCCore):
                 nphases        = 4,
                 sys_clk_freq   = sys_clk_freq)
             self.add_sdram("sdram",
-                phy              = self.ddrphy,
-                module           = MT41K64M16(sys_clk_freq, "1:4"),
-                l2_cache_size    = kwargs.get("l2_size", 8192),
-                l2_cache_reverse = False,
+                phy           = self.ddrphy,
+                module        = MT41K64M16(sys_clk_freq, "1:4"),
+                l2_cache_size = kwargs.get("l2_size", 8192)
             )
 
         # Etherbone --------------------------------------------------------------------------------