diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py
index 8a80ba4..57fe66a 100755
--- a/litex_boards/targets/genesys2.py
+++ b/litex_boards/targets/genesys2.py
@@ -56,7 +56,8 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
                 memtype      = "DDR3",
                 nphases      = 4,
-                sys_clk_freq = sys_clk_freq)
+                sys_clk_freq = sys_clk_freq,
+                cmd_latency  = 1)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py
index fef1b4e..ec8f59e 100755
--- a/litex_boards/targets/kcu105.py
+++ b/litex_boards/targets/kcu105.py
@@ -68,7 +68,6 @@ class BaseSoC(SoCCore):
                 iodelay_clk_freq = 200e6,
                 cmd_latency      = 1)
             self.add_csr("ddrphy")
-            self.add_constant("USDDRPHY_DEBUG")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
                 module                  = EDY4016A(sys_clk_freq, "1:4"),
diff --git a/litex_boards/targets/kx2.py b/litex_boards/targets/kx2.py
index 66c1068..595d311 100755
--- a/litex_boards/targets/kx2.py
+++ b/litex_boards/targets/kx2.py
@@ -56,7 +56,8 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = s7ddrphy.K7DDRPHY(platform.request("ddram"),
                 memtype      = "DDR3",
                 nphases      = 4,
-                sys_clk_freq = sys_clk_freq)
+                sys_clk_freq = sys_clk_freq,
+                cmd_latency  = 1)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py
index ff5f694..a766557 100755
--- a/litex_boards/targets/mercury_xu5.py
+++ b/litex_boards/targets/mercury_xu5.py
@@ -65,9 +65,8 @@ class BaseSoC(SoCCore):
                 memtype          = "DDR4",
                 sys_clk_freq     = sys_clk_freq,
                 iodelay_clk_freq = 500e6,
-                cmd_latency      = 0)
+                cmd_latency      = 1)
             self.add_csr("ddrphy")
-            self.add_constant("USDDRPHY_DEBUG")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
                 module                  = MT40A256M16(sys_clk_freq, "1:4"),
diff --git a/litex_boards/targets/vc707.py b/litex_boards/targets/vc707.py
index 0f7f4db..fb2e845 100755
--- a/litex_boards/targets/vc707.py
+++ b/litex_boards/targets/vc707.py
@@ -56,7 +56,8 @@ class BaseSoC(SoCCore):
             self.submodules.ddrphy = s7ddrphy.V7DDRPHY(platform.request("ddram"),
                 memtype      = "DDR3",
                 nphases      = 4,
-                sys_clk_freq = sys_clk_freq)
+                sys_clk_freq = sys_clk_freq,
+                cmd_latency  = 1)
             self.add_csr("ddrphy")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py
index b71fd32..d6a40d1 100755
--- a/litex_boards/targets/vcu118.py
+++ b/litex_boards/targets/vcu118.py
@@ -65,9 +65,8 @@ class BaseSoC(SoCCore):
                 memtype          = "DDR4",
                 sys_clk_freq     = sys_clk_freq,
                 iodelay_clk_freq = 500e6,
-                cmd_latency      = 0)
+                cmd_latency      = 1)
             self.add_csr("ddrphy")
-            self.add_constant("USDDRPHY_DEBUG")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
                 module                  = EDY4016A(sys_clk_freq, "1:4"),
diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py
index 3bcb037..1fcc688 100755
--- a/litex_boards/targets/zcu104.py
+++ b/litex_boards/targets/zcu104.py
@@ -66,7 +66,6 @@ class BaseSoC(SoCCore):
                 iodelay_clk_freq = 500e6,
                 cmd_latency      = 1)
             self.add_csr("ddrphy")
-            self.add_constant("USDDRPHY_DEBUG")
             self.add_sdram("sdram",
                 phy                     = self.ddrphy,
                 module                  = MTA4ATF51264HZ(sys_clk_freq, "1:4"),