diff --git a/litex_boards/__init__.py b/litex_boards/__init__.py
index cd33b53..1edcb48 100644
--- a/litex_boards/__init__.py
+++ b/litex_boards/__init__.py
@@ -18,6 +18,7 @@ vendors = [
     "fairwaves",
     "hackaday",
     "kosagi",
+    "krtkl",
     "lattice",
     "lambdaconcept",
     "linsn",
diff --git a/litex_boards/platforms/snickerdoodle.py b/litex_boards/platforms/krtkl_snickerdoodle.py
similarity index 88%
rename from litex_boards/platforms/snickerdoodle.py
rename to litex_boards/platforms/krtkl_snickerdoodle.py
index 3e550a2..b182a12 100644
--- a/litex_boards/platforms/snickerdoodle.py
+++ b/litex_boards/platforms/krtkl_snickerdoodle.py
@@ -1,8 +1,8 @@
 #
 # This file is part of LiteX-Boards.
 #
+# Copyright (c) 2021 Derek Mulcahy <derekmulcahy@gmail.com>
 # Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
-# Copyright (c) 2021 Derek Mulcahy <derekmulcahy@gmail.com>,
 # SPDX-License-Identifier: BSD-2-Clause
 
 from litex.build.generic_platform import *
@@ -11,13 +11,13 @@ from litex.build.xilinx import XilinxPlatform, VivadoProgrammer
 # IOs ----------------------------------------------------------------------------------------------
 
 _io = [
-    # Clk / Rst - A placeholder for an external clock
+    # Clk / Rst - FIXME: A placeholder for an external clock
     ("clk100", 0, Pins("H16"), IOStandard("LVCMOS33")),
 
-    # Leds - A placeholder for an external LED
+    # Leds - FIXME: A placeholder for an external LED
     ("user_led", 0, Pins("G14"), IOStandard("LVCMOS33")),
 
-    # UART - A placeholder for an external UART
+    # UART - FIXME: A placeholder for an external UART
     ("serial", 0,
         Subsignal("tx", Pins("D19")),
         Subsignal("rx", Pins("D20")),
@@ -73,11 +73,13 @@ class Platform(XilinxPlatform):
     def __init__(self):
         XilinxPlatform.__init__(self, "xc7z010-clg400-1", _io,  _connectors, toolchain="vivado")
         self.default_clk_period = 1e9 / self.default_clk_freq
+        self.toolchain.bitstream_commands = [
+            "set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]"
+        ]
 
     def create_programmer(self):
         return VivadoProgrammer(flash_part="n25q128a")
 
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
-        self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True),
-                                   self.default_clk_period)
+        self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True), self.default_clk_period)
diff --git a/litex_boards/targets/snickerdoodle.py b/litex_boards/targets/krtkl_snickerdoodle.py
similarity index 90%
rename from litex_boards/targets/snickerdoodle.py
rename to litex_boards/targets/krtkl_snickerdoodle.py
index ba484c3..0479636 100755
--- a/litex_boards/targets/snickerdoodle.py
+++ b/litex_boards/targets/krtkl_snickerdoodle.py
@@ -3,8 +3,8 @@
 #
 # This file is part of LiteX-Boards.
 #
-# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>,
-# Copyright (c) 2021 Derek Mulcahy <derekmulcahy@gmail.com>,
+# Copyright (c) 2021 Derek Mulcahy <derekmulcahy@gmail.com>
+# Copyright (c) 2019-2020 Florent Kermarrec <florent@enjoy-digital.fr>
 # SPDX-License-Identifier: BSD-2-Clause
 
 import os
@@ -63,12 +63,10 @@ class _CRG(Module):
 
 class BaseSoC(SoCCore):
 
-    def __init__(self,
-                 sys_clk_freq    = int(100e6),
-                 ext_clk_freq    = None,
-                 with_led_chaser = True,
-                 xci_file        = None,
-                 **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), with_led_chaser=True,
+        ext_clk_freq = None,
+        xci_file     = None,
+        **kwargs):
 
         platform = snickerdoodle.Platform()
 
@@ -77,11 +75,9 @@ class BaseSoC(SoCCore):
             platform.default_clk_period = 1e9 / ext_clk_freq
 
         if kwargs.get("cpu_type", None) == "zynq7000":
-            kwargs['integrated_sram_size'] = 0
-            kwargs['with_uart'] = False
-            self.mem_map = {
-                'csr': 0x4000_0000,  # Zynq GP0 default
-            }
+            kwargs["integrated_sram_size"] = 0
+            kwargs["with_uart"]            = False
+            self.mem_map = {"csr": 0x4000_0000}  # Zynq GP0 default
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
@@ -108,8 +104,6 @@ class BaseSoC(SoCCore):
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq, use_ps7_clk)
 
-        platform.add_platform_command("set_property BITSTREAM.GENERAL.COMPRESS True [current_design]")
-
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
             self.submodules.leds = LedChaser(