From dc925846817f73212c75598a8a548b8df8875211 Mon Sep 17 00:00:00 2001 From: Sylvain Munaut Date: Tue, 22 Mar 2022 23:36:41 +0100 Subject: [PATCH] adi_adrv2crr: Upgrade part to speedgrade 2 Even though the schematic and bom call for speedgrade 1, this was only for the prototypes. All productions units have been updated to speedgrade 2. See this thread: https://ez.analog.com/fpga/f/q-a/112356/adrv9009-zu11eg-speed-grade And the official HDL project for the board: https://github.com/analogdevicesinc/hdl/blob/master/projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl#L16 Signed-off-by: Sylvain Munaut --- litex_boards/platforms/adi_adrv2crr_fmc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/platforms/adi_adrv2crr_fmc.py b/litex_boards/platforms/adi_adrv2crr_fmc.py index 008ca62..e01b5d0 100644 --- a/litex_boards/platforms/adi_adrv2crr_fmc.py +++ b/litex_boards/platforms/adi_adrv2crr_fmc.py @@ -476,7 +476,7 @@ class Platform(XilinxPlatform): default_clk_period = 1e9/122.88e6 def __init__(self): - XilinxPlatform.__init__(self, "xczu11eg-ffvf1517-1-i", _io, _connectors, toolchain="vivado") + XilinxPlatform.__init__(self, "xczu11eg-ffvf1517-2-i", _io, _connectors, toolchain="vivado") def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment)