diff --git a/litex_boards/platforms/ulx3s.py b/litex_boards/platforms/ulx3s.py
index e8f0860..5553091 100644
--- a/litex_boards/platforms/ulx3s.py
+++ b/litex_boards/platforms/ulx3s.py
@@ -10,7 +10,7 @@ from litex.build.lattice.programmer import UJProg
 
 # IOs ----------------------------------------------------------------------------------------------
 
-_io = [
+_io_common = [
     ("clk25", 0, Pins("G2"), IOStandard("LVCMOS33")),
     ("rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
 
@@ -28,25 +28,6 @@ _io = [
         Subsignal("rx", Pins("M1"), IOStandard("LVCMOS33"))
     ),
 
-    ("spisdcard", 0,
-        Subsignal("clk",  Pins("H2")),
-        Subsignal("mosi", Pins("J1"), Misc("PULLMODE=UP")),
-        Subsignal("cs_n", Pins("K2"), Misc("PULLMODE=UP")),
-        Subsignal("miso", Pins("J3"), Misc("PULLMODE=UP")),
-        Misc("SLEWRATE=FAST"),
-        IOStandard("LVCMOS33"),
-    ),
-
-    ("sdcard", 0,
-        Subsignal("clk",  Pins("H2")),
-        Subsignal("cmd",  Pins("J1"), Misc("PULLMODE=UP")),
-        Subsignal("data", Pins("J3 H1 K1 K2"), Misc("PULLMODE=UP")),
-        Subsignal("cd", Pins("N5")),
-        Subsignal("wp", Pins("P5")),
-        Misc("SLEWRATE=FAST"),
-        IOStandard("LVCMOS33"),
-    ),
-
     ("sdram_clock", 0, Pins("F19"), IOStandard("LVCMOS33")),
     ("sdram", 0,
         Subsignal("a",     Pins(
@@ -111,14 +92,56 @@ _io = [
     ),
 ]
 
+_io_1_7 = [
+    ("spisdcard", 0,
+        Subsignal("clk",  Pins("J1")),
+        Subsignal("mosi", Pins("J3"), Misc("PULLMODE=UP")),
+        Subsignal("cs_n", Pins("H1"), Misc("PULLMODE=UP")),
+        Subsignal("miso", Pins("K2"), Misc("PULLMODE=UP")),
+        Misc("SLEWRATE=FAST"),
+        IOStandard("LVCMOS33"),
+    ),
+
+    ("sdcard", 0,
+        Subsignal("clk",  Pins("J1")),
+        Subsignal("cmd",  Pins("J3"), Misc("PULLMODE=UP")),
+        Subsignal("data", Pins("K2 K1 H2 H1"), Misc("PULLMODE=UP")),
+        Misc("SLEWRATE=FAST"),
+        IOStandard("LVCMOS33"),
+    ),
+]
+
+_io_2_0 = [
+    ("spisdcard", 0,
+        Subsignal("clk",  Pins("H2")),
+        Subsignal("mosi", Pins("J1"), Misc("PULLMODE=UP")),
+        Subsignal("cs_n", Pins("K2"), Misc("PULLMODE=UP")),
+        Subsignal("miso", Pins("J3"), Misc("PULLMODE=UP")),
+        Misc("SLEWRATE=FAST"),
+        IOStandard("LVCMOS33"),
+    ),
+
+    ("sdcard", 0,
+        Subsignal("clk",  Pins("H2")),
+        Subsignal("cmd",  Pins("J1"), Misc("PULLMODE=UP")),
+        Subsignal("data", Pins("J3 H1 K1 K2"), Misc("PULLMODE=UP")),
+        Subsignal("cd", Pins("N5")),
+        Subsignal("wp", Pins("P5")),
+        Misc("SLEWRATE=FAST"),
+        IOStandard("LVCMOS33"),
+    ),
+]
+
 # Platform -----------------------------------------------------------------------------------------
 
 class Platform(LatticePlatform):
     default_clk_name   = "clk25"
     default_clk_period = 1e9/25e6
 
-    def __init__(self, device="LFE5U-45F", **kwargs):
+    def __init__(self, device="LFE5U-45F", revision="2.0", **kwargs):
         assert device in ["LFE5U-25F", "LFE5U-45F", "LFE5U-85F"]
+        assert revision in ["1.7", "2.0"]
+        _io = _io_common + {"1.7": _io_1_7, "2.0": _io_2_0}[revision]
         LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs)
 
     def create_programmer(self):
diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py
index ad6de73..316d668 100755
--- a/litex_boards/targets/ulx3s.py
+++ b/litex_boards/targets/ulx3s.py
@@ -79,10 +79,10 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, device="LFE5U-45F", toolchain="trellis",
+    def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis",
         sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1", **kwargs):
 
-        platform = ulx3s.Platform(device=device, toolchain=toolchain)
+        platform = ulx3s.Platform(device=device, revision=revision, toolchain=toolchain)
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
@@ -132,6 +132,7 @@ def main():
     parser.add_argument("--load",  action="store_true", help="Load bitstream")
     parser.add_argument("--toolchain", default="trellis",   help="Gateware toolchain to use, trellis (default) or diamond")
     parser.add_argument("--device",             dest="device",    default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F")
+    parser.add_argument("--revision", default="2.0", type=str,  help="Board revision 2.0 (default), 1.7")
     parser.add_argument("--sys-clk-freq", default=50e6,           help="System clock frequency (default=50MHz)")
     parser.add_argument("--sdram-module", default="MT48LC16M16",  help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
     parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
@@ -143,7 +144,7 @@ def main():
     trellis_args(parser)
     args = parser.parse_args()
 
-    soc = BaseSoC(device=args.device, toolchain=args.toolchain,
+    soc = BaseSoC(device=args.device, revision=args.revision, toolchain=args.toolchain,
         sys_clk_freq     = int(float(args.sys_clk_freq)),
         sdram_module_cls = args.sdram_module,
         sdram_rate       = args.sdram_rate,