From de09b10726238122edbee9353f621d4b6cfd4523 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 24 Sep 2020 18:19:49 +0200 Subject: [PATCH] targets/xcu1525: add ddram-channel selection and rewrite DRC workaround comment. --- litex_boards/targets/xcu1525.py | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/litex_boards/targets/xcu1525.py b/litex_boards/targets/xcu1525.py index a43f42a..074f33b 100755 --- a/litex_boards/targets/xcu1525.py +++ b/litex_boards/targets/xcu1525.py @@ -88,8 +88,7 @@ class BaseSoC(SoCCore): l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_reverse = True ) - # FIXME: Vivado DRC error because T of ODERDESE3 directly connected to IOBUF but not I - # (since ODELAYE3 in-between), understand if this can be DRC rule can be safely disabled. + # Workadound for Vivado 2018.2 DRC, can be ignored and probably fixed on newer Vivado versions. platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks PDCN-2736]") # PCIe ------------------------------------------------------------------------------------- @@ -139,10 +138,11 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on XCU1525") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") - parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") - parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--ddram-channel", default="0", help="DDRAM channel") + parser.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") + parser.add_argument("--driver", action="store_true", help="Generate PCIe driver") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() @@ -150,7 +150,10 @@ def main(): # Enforce arguments args.csr_data_width = 32 - soc = BaseSoC(with_pcie=args.with_pcie, **soc_sdram_argdict(args)) + soc = BaseSoC( + ddram_channel = int(args.ddram_channel, 0), + with_pcie = args.with_pcie, + **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build)