From de4ad324cbbf0af126664f65693b9a7eb4a31c9c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 30 Sep 2021 18:03:13 +0200 Subject: [PATCH] mnt_rkx7: Revert default sys_clk_freq to 100MHz. --- litex_boards/targets/mnt_rkx7.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/mnt_rkx7.py b/litex_boards/targets/mnt_rkx7.py index 14336b2..dd94136 100755 --- a/litex_boards/targets/mnt_rkx7.py +++ b/litex_boards/targets/mnt_rkx7.py @@ -47,7 +47,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, + def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, with_spi_flash=False, **kwargs): platform = mnt_rkx7.Platform() @@ -99,7 +99,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on MNT-RKX7") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)") sdopts = parser.add_mutually_exclusive_group() sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")