From debafd7c173294a9310a0557feab55fa44878c94 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 12 Jul 2019 19:19:01 +0200 Subject: [PATCH] official/partner: update --- litex_boards/official/platforms/arty.py | 12 ++++++------ litex_boards/official/platforms/avalanche.py | 2 +- litex_boards/official/platforms/de0nano.py | 2 +- litex_boards/official/platforms/genesys2.py | 3 +++ litex_boards/official/platforms/kc705.py | 4 ++++ litex_boards/official/platforms/kcu105.py | 3 +++ litex_boards/official/platforms/machxo3.py | 2 +- litex_boards/official/platforms/nexys4ddr.py | 2 +- litex_boards/official/platforms/nexys_video.py | 2 +- litex_boards/official/platforms/versa_ecp3.py | 2 +- litex_boards/official/platforms/versa_ecp5.py | 3 ++- litex_boards/official/targets/arty.py | 8 +++++--- litex_boards/official/targets/de0nano.py | 3 +++ litex_boards/official/targets/genesys2.py | 8 +++++--- litex_boards/official/targets/kc705.py | 10 +++++++--- litex_boards/official/targets/kcu105.py | 8 +++++--- litex_boards/official/targets/minispartan6.py | 5 +++++ litex_boards/official/targets/nexys4ddr.py | 8 +++++--- litex_boards/official/targets/nexys_video.py | 8 +++++--- litex_boards/official/targets/versa_ecp5.py | 9 ++++++--- litex_boards/partner/platforms/netv2.py | 2 ++ litex_boards/partner/platforms/tinyfpga_bx.py | 4 ++++ litex_boards/partner/platforms/ulx3s.py | 2 +- litex_boards/partner/targets/netv2.py | 8 +++++--- litex_boards/partner/targets/ulx3s.py | 6 +++++- 25 files changed, 87 insertions(+), 39 deletions(-) diff --git a/litex_boards/official/platforms/arty.py b/litex_boards/official/platforms/arty.py index 36d64a3..2e5af33 100644 --- a/litex_boards/official/platforms/arty.py +++ b/litex_boards/official/platforms/arty.py @@ -1,7 +1,5 @@ -# This file is Copyright (c) 2015 Yann Sionneau -# This file is Copyright (c) 2015 Florent Kermarrec -# This file is Copyright (c) 2018 William D. Jones -# This file is Copyright (c) 2018 Caleb Jamison +# This file is Copyright (c) 2015 Yann Sionneau +# This file is Copyright (c) 2015-2019 Florent Kermarrec # License: BSD from litex.build.generic_platform import * @@ -79,13 +77,15 @@ _io = [ IOStandard("LVCMOS33"), ), - ("spiflash4x", 0, # clock needs to be accessed through STARTUPE2 + ("spiflash4x", 0, Subsignal("cs_n", Pins("L13")), + Subsignal("clk", Pins("L16")), Subsignal("dq", Pins("K17", "K18", "L14", "M14")), IOStandard("LVCMOS33") ), - ("spiflash", 0, # clock needs to be accessed through STARTUPE2 + ("spiflash", 0, Subsignal("cs_n", Pins("L13")), + Subsignal("clk", Pins("L16")), Subsignal("mosi", Pins("K17")), Subsignal("miso", Pins("K18")), Subsignal("wp", Pins("L14")), diff --git a/litex_boards/official/platforms/avalanche.py b/litex_boards/official/platforms/avalanche.py index 2f4b13a..a28fb44 100644 --- a/litex_boards/official/platforms/avalanche.py +++ b/litex_boards/official/platforms/avalanche.py @@ -1,4 +1,4 @@ -# This file is Copyright (c) 2018 Florent Kermarrec +# This file is Copyright (c) 2018-2019 Florent Kermarrec # License: BSD from litex.build.generic_platform import * diff --git a/litex_boards/official/platforms/de0nano.py b/litex_boards/official/platforms/de0nano.py index 2581eac..5328f61 100644 --- a/litex_boards/official/platforms/de0nano.py +++ b/litex_boards/official/platforms/de0nano.py @@ -1,4 +1,4 @@ -# This file is Copyright (c) 2013 Florent Kermarrec +# This file is Copyright (c) 2014-2019 Florent Kermarrec # License: BSD from litex.build.generic_platform import * diff --git a/litex_boards/official/platforms/genesys2.py b/litex_boards/official/platforms/genesys2.py index 1efdf1f..a86fc48 100644 --- a/litex_boards/official/platforms/genesys2.py +++ b/litex_boards/official/platforms/genesys2.py @@ -1,3 +1,6 @@ +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# License: BSD + from litex.build.generic_platform import * from litex.build.xilinx import XilinxPlatform, VivadoProgrammer diff --git a/litex_boards/official/platforms/kc705.py b/litex_boards/official/platforms/kc705.py index 6584092..54ea3e6 100644 --- a/litex_boards/official/platforms/kc705.py +++ b/litex_boards/official/platforms/kc705.py @@ -1,3 +1,7 @@ +# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq +# This file is Copyright (c) 2014-2019 Florent Kermarrec +# This file is Copyright (c) 2015 Yann Sionneau + from litex.build.generic_platform import * from litex.build.xilinx import XilinxPlatform, VivadoProgrammer diff --git a/litex_boards/official/platforms/kcu105.py b/litex_boards/official/platforms/kcu105.py index eccc495..4cf6fb1 100644 --- a/litex_boards/official/platforms/kcu105.py +++ b/litex_boards/official/platforms/kcu105.py @@ -1,3 +1,6 @@ +# This file is Copyright (c) 2017-2019 Florent Kermarrec +# License: BSD + from litex.build.generic_platform import * from litex.build.xilinx import XilinxPlatform, VivadoProgrammer diff --git a/litex_boards/official/platforms/machxo3.py b/litex_boards/official/platforms/machxo3.py index e2e96fd..ec4d734 100644 --- a/litex_boards/official/platforms/machxo3.py +++ b/litex_boards/official/platforms/machxo3.py @@ -1,4 +1,4 @@ -# This file is Copyright (c) 2016 Florent Kermarrec +# This file is Copyright (c) 2016-2019 Florent Kermarrec # License: BSD from litex.build.generic_platform import * diff --git a/litex_boards/official/platforms/nexys4ddr.py b/litex_boards/official/platforms/nexys4ddr.py index e14e19d..3d0e759 100644 --- a/litex_boards/official/platforms/nexys4ddr.py +++ b/litex_boards/official/platforms/nexys4ddr.py @@ -1,4 +1,4 @@ -# This file is Copyright (c) 2018 Florent Kermarrec +# This file is Copyright (c) 2018-2019 Florent Kermarrec # License: BSD from litex.build.generic_platform import * diff --git a/litex_boards/official/platforms/nexys_video.py b/litex_boards/official/platforms/nexys_video.py index 4a49423..fd7bb35 100644 --- a/litex_boards/official/platforms/nexys_video.py +++ b/litex_boards/official/platforms/nexys_video.py @@ -1,4 +1,4 @@ -# This file is Copyright (c) 2015 Florent Kermarrec +# This file is Copyright (c) 2015-2019 Florent Kermarrec # License: BSD from litex.build.generic_platform import * diff --git a/litex_boards/official/platforms/versa_ecp3.py b/litex_boards/official/platforms/versa_ecp3.py index 2d7a0b0..6013da6 100644 --- a/litex_boards/official/platforms/versa_ecp3.py +++ b/litex_boards/official/platforms/versa_ecp3.py @@ -1,4 +1,4 @@ -# This file is Copyright (c) 2013 Florent Kermarrec +# This file is Copyright (c) 2015-2019 Florent Kermarrec # License: BSD from litex.build.generic_platform import * diff --git a/litex_boards/official/platforms/versa_ecp5.py b/litex_boards/official/platforms/versa_ecp5.py index 626eabe..b91110b 100644 --- a/litex_boards/official/platforms/versa_ecp5.py +++ b/litex_boards/official/platforms/versa_ecp5.py @@ -1,4 +1,5 @@ -# This file is Copyright (c) 2017 Serge 'q3k' Bazanski +# This file is Copyright (c) 2017 Sergiusz Bazanski +# This file is Copyright (c) 2018-2019 Florent Kermarrec # License: BSD from litex.build.generic_platform import * diff --git a/litex_boards/official/targets/arty.py b/litex_boards/official/targets/arty.py index d28e150..184186f 100755 --- a/litex_boards/official/targets/arty.py +++ b/litex_boards/official/targets/arty.py @@ -1,5 +1,8 @@ #!/usr/bin/env python3 +# This file is Copyright (c) 2015-2019 Florent Kermarrec +# License: BSD + import argparse from migen import * @@ -7,7 +10,6 @@ from migen import * from litex_boards.official.platforms import arty from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -15,7 +17,7 @@ from litedram.modules import MT41K128M16 from litedram.phy import s7ddrphy from liteeth.phy.mii import LiteEthPHYMII -from liteeth.core.mac import LiteEthMAC +from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -82,7 +84,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/de0nano.py b/litex_boards/official/targets/de0nano.py index a80480f..5b635b0 100755 --- a/litex_boards/official/targets/de0nano.py +++ b/litex_boards/official/targets/de0nano.py @@ -1,5 +1,8 @@ #!/usr/bin/env python3 +# This file is Copyright (c) 2015-2019 Florent Kermarrec +# License: BSD + import argparse from migen import * diff --git a/litex_boards/official/targets/genesys2.py b/litex_boards/official/targets/genesys2.py index ba73493..c1390ff 100755 --- a/litex_boards/official/targets/genesys2.py +++ b/litex_boards/official/targets/genesys2.py @@ -1,5 +1,8 @@ #!/usr/bin/env python3 +# This file is Copyright (c) 2019 Florent Kermarrec +# License: BSD + import argparse from migen import * @@ -7,7 +10,6 @@ from migen import * from litex_boards.official.platforms import genesys2 from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -15,7 +17,7 @@ from litedram.modules import MT41J256M16 from litedram.phy import s7ddrphy from liteeth.phy.s7rgmii import LiteEthPHYRGMII -from liteeth.core.mac import LiteEthMAC +from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -75,7 +77,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/kc705.py b/litex_boards/official/targets/kc705.py index 40ff577..622d8e4 100755 --- a/litex_boards/official/targets/kc705.py +++ b/litex_boards/official/targets/kc705.py @@ -1,5 +1,10 @@ #!/usr/bin/env python3 +# This file is Copyright (c) 2014-2015 Sebastien Bourdeauducq +# This file is Copyright (c) 2014-2019 Florent Kermarrec +# This file is Copyright (c) 2014-2015 Yann Sionneau +# License: BSD + import argparse from migen import * @@ -7,7 +12,6 @@ from migen import * from litex_boards.official.platforms import kc705 from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -15,7 +19,7 @@ from litedram.modules import MT8JTF12864 from litedram.phy import s7ddrphy from liteeth.phy import LiteEthPHY -from liteeth.core.mac import LiteEthMAC +from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -75,7 +79,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/kcu105.py b/litex_boards/official/targets/kcu105.py index a537d6c..7a5a638 100755 --- a/litex_boards/official/targets/kcu105.py +++ b/litex_boards/official/targets/kcu105.py @@ -1,5 +1,8 @@ #!/usr/bin/env python3 +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# License: BSD + import argparse from migen import * @@ -7,7 +10,6 @@ from migen import * from litex_boards.official.platforms import kcu105 from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -15,7 +17,7 @@ from litedram.modules import EDY4016A from litedram.phy import usddrphy from liteeth.phy.ku_1000basex import KU_1000BASEX -from liteeth.core.mac import LiteEthMAC +from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -114,7 +116,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/minispartan6.py b/litex_boards/official/targets/minispartan6.py index 9a1f433..02d8520 100755 --- a/litex_boards/official/targets/minispartan6.py +++ b/litex_boards/official/targets/minispartan6.py @@ -1,5 +1,10 @@ #!/usr/bin/env python3 +# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq +# This file is Copyright (c) 2014-2019 Florent Kermarrec +# This file is Copyright (c) 2014 Yann Sionneau +# License: BSD + import argparse from fractions import Fraction diff --git a/litex_boards/official/targets/nexys4ddr.py b/litex_boards/official/targets/nexys4ddr.py index 5869d74..1eeef49 100755 --- a/litex_boards/official/targets/nexys4ddr.py +++ b/litex_boards/official/targets/nexys4ddr.py @@ -1,5 +1,8 @@ #!/usr/bin/env python3 +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# License: BSD + import argparse from migen import * @@ -7,7 +10,6 @@ from migen import * from litex_boards.official.platforms import nexys4ddr from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -15,7 +17,7 @@ from litedram.modules import MT47H64M16 from litedram.phy import s7ddrphy from liteeth.phy.rmii import LiteEthPHYRMII -from liteeth.core.mac import LiteEthMAC +from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -81,7 +83,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/nexys_video.py b/litex_boards/official/targets/nexys_video.py index 526db92..d80d9b8 100755 --- a/litex_boards/official/targets/nexys_video.py +++ b/litex_boards/official/targets/nexys_video.py @@ -1,5 +1,8 @@ #!/usr/bin/env python3 +# This file is Copyright (c) 2015-2019 Florent Kermarrec +# License: BSD + import argparse from migen import * @@ -7,7 +10,6 @@ from migen import * from litex_boards.official.platforms import nexys_video from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -15,7 +17,7 @@ from litedram.modules import MT41K256M16 from litedram.phy import s7ddrphy from liteeth.phy.s7rgmii import LiteEthPHYRGMII -from liteeth.core.mac import LiteEthMAC +from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -79,7 +81,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/official/targets/versa_ecp5.py b/litex_boards/official/targets/versa_ecp5.py index 42217c9..5dc8a57 100755 --- a/litex_boards/official/targets/versa_ecp5.py +++ b/litex_boards/official/targets/versa_ecp5.py @@ -1,5 +1,9 @@ #!/usr/bin/env python3 +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# This file is Copyright (c) 2018-2019 David Shah +# License: BSD + import argparse from migen import * @@ -8,7 +12,6 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex_boards.official.platforms import versa_ecp5 from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -16,7 +19,7 @@ from litedram.modules import MT41K64M16 from litedram.phy import ECP5DDRPHY from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII -from liteeth.core.mac import LiteEthMAC +from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -112,7 +115,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/partner/platforms/netv2.py b/litex_boards/partner/platforms/netv2.py index 7098664..f2b52c4 100644 --- a/litex_boards/partner/platforms/netv2.py +++ b/litex_boards/partner/platforms/netv2.py @@ -1,3 +1,5 @@ +# This file is Copyright (c) 2019 Florent Kermarrec +# License: BSD from litex.build.generic_platform import * from litex.build.xilinx import XilinxPlatform, VivadoProgrammer diff --git a/litex_boards/partner/platforms/tinyfpga_bx.py b/litex_boards/partner/platforms/tinyfpga_bx.py index e459188..91ae840 100644 --- a/litex_boards/partner/platforms/tinyfpga_bx.py +++ b/litex_boards/partner/platforms/tinyfpga_bx.py @@ -1,3 +1,7 @@ +# This file is Copyright (c) 2018 William D. Jones +# This file is Copyright (c) 2019 Florent Kermarrec +# License: BSD + from litex.build.generic_platform import * from litex.build.lattice import LatticePlatform from litex.build.lattice.programmer import TinyProgProgrammer diff --git a/litex_boards/partner/platforms/ulx3s.py b/litex_boards/partner/platforms/ulx3s.py index 2a7f6d8..1d9e964 100644 --- a/litex_boards/partner/platforms/ulx3s.py +++ b/litex_boards/partner/platforms/ulx3s.py @@ -1,4 +1,4 @@ -# This file is Copyright (c) 2018 Florent Kermarrec +# This file is Copyright (c) 2018-2019 Florent Kermarrec # License: BSD from litex.build.generic_platform import * diff --git a/litex_boards/partner/targets/netv2.py b/litex_boards/partner/targets/netv2.py index 63b2069..adea646 100755 --- a/litex_boards/partner/targets/netv2.py +++ b/litex_boards/partner/targets/netv2.py @@ -1,5 +1,8 @@ #!/usr/bin/env python3 +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# License: BSD + import argparse from migen import * @@ -7,7 +10,6 @@ from migen import * from litex_boards.partner.platforms import netv2 from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -15,7 +17,7 @@ from litedram.modules import MT41J128M16 from litedram.phy import s7ddrphy from liteeth.phy.rmii import LiteEthPHYRMII -from liteeth.core.mac import LiteEthMAC +from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -79,7 +81,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex_boards/partner/targets/ulx3s.py b/litex_boards/partner/targets/ulx3s.py index 63d94f9..b126e9a 100755 --- a/litex_boards/partner/targets/ulx3s.py +++ b/litex_boards/partner/targets/ulx3s.py @@ -1,5 +1,9 @@ #!/usr/bin/env python3 +# This file is Copyright (c) 2018-2019 Florent Kermarrec +# This file is Copyright (c) 2018 David Shah +# License: BSD + import argparse from migen import * @@ -59,7 +63,7 @@ class BaseSoC(SoCSDRAM): self.submodules.crg = _CRG(platform, sys_clk_freq) if not self.integrated_main_ram_size: - self.submodules.sdrphy = GENSDRPHY(platform.request("sdram")) + self.submodules.sdrphy = GENSDRPHY(platform.request("sdram"), cl=3) sdram_module = MT48LC16M16(sys_clk_freq, "1:1") self.register_sdram(self.sdrphy, sdram_module.geom_settings,