From ded90748ee7d2d3ca2dc9aea0199703fcdcc959b Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 27 Mar 2024 08:48:05 +0100 Subject: [PATCH] xilinx_kc705: Minor Cleanup/Update. --- litex_boards/platforms/xilinx_kc705.py | 8 ++++---- litex_boards/targets/xilinx_kc705.py | 10 ++++++++-- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/litex_boards/platforms/xilinx_kc705.py b/litex_boards/platforms/xilinx_kc705.py index 49abebf..9506e50 100644 --- a/litex_boards/platforms/xilinx_kc705.py +++ b/litex_boards/platforms/xilinx_kc705.py @@ -95,10 +95,10 @@ _io = [ "AB19 AD16 AC19 AD17 AA18 AB18 AE18 AD18", "AG19 AK19 AG18 AF18 AH19 AJ19 AE19 AD19", "AK16 AJ17 AG15 AF15 AH17 AG14 AH15 AK15", - "AK8 AK6 AG7 AF7 AF8 AK4 AJ8 AJ6", - "AH5 AH6 AJ2 AH2 AH4 AJ4 AK1 AJ1", - "AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5", - "AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"), + " AK8 AK6 AG7 AF7 AF8 AK4 AJ8 AJ6", + " AH5 AH6 AJ2 AH2 AH4 AJ4 AK1 AJ1", + " AF1 AF2 AE4 AE3 AF3 AF5 AE1 AE5", + " AC1 AD3 AC4 AC5 AE6 AD6 AC2 AD4"), IOStandard("SSTL15_T_DCI")), Subsignal("dqs_p", Pins("AC16 Y19 AJ18 AH16 AH7 AG2 AG4 AD2"), IOStandard("DIFF_SSTL15")), diff --git a/litex_boards/targets/xilinx_kc705.py b/litex_boards/targets/xilinx_kc705.py index 03158bc..1c95ee8 100755 --- a/litex_boards/targets/xilinx_kc705.py +++ b/litex_boards/targets/xilinx_kc705.py @@ -40,14 +40,20 @@ class _CRG(LiteXModule): # # # + # Clk/Rst. + clk200 = platform.request("clk200") + rst = platform.request("cpu_reset") + + # PLL. self.pll = pll = S7MMCM(speedgrade=-2) - self.comb += pll.reset.eq(platform.request("cpu_reset") | self.rst) - pll.register_clkin(platform.request("clk200"), 200e6) + self.comb += pll.reset.eq(rst | self.rst) + pll.register_clkin(clk200, 200e6) pll.create_clkout(self.cd_sys, sys_clk_freq) pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_idelay, 200e6) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. + # IDelayCtrl. self.idelayctrl = S7IDELAYCTRL(self.cd_idelay) # BaseSoC ------------------------------------------------------------------------------------------