diff --git a/litex_boards/targets/siglent_sds1104xe.py b/litex_boards/targets/siglent_sds1104xe.py
index 86783ab..ac1ec9b 100755
--- a/litex_boards/targets/siglent_sds1104xe.py
+++ b/litex_boards/targets/siglent_sds1104xe.py
@@ -84,7 +84,7 @@ class BaseSoC(SoCCore):
         # DDR3 SDRAM -------------------------------------------------------------------------------
         if not self.integrated_main_ram_size:
             self.submodules.ddrphy = s7ddrphy.A7DDRPHY(
-                pads           = PHYPadsReducer(platform.request("ddram"), [0, 1]), # FIXME: Reduce to 16-bit for use with NaxRiscv.
+                pads           = PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]),
                 memtype        = "DDR3",
                 nphases        = 4,
                 sys_clk_freq   = sys_clk_freq)